IVTAD
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| IVTADU[4:0] | |||||||
| Access | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | ||
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| IVTADH[7:0] | |||||||
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IVTADL[7:0] | |||||||
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Interrupt Vector Table Address Most Significant 5 bits
Interrupt Vector Table Address Middle 8 bits
Interrupt Vector Table Address Least Significant 8 bits