SPIxINTF
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SRMTIF | TCZIF | SOSIF | EOSIF | RXOIF | TXUIF | ||
| AccessR/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | ||
| Reset0 | 0 | 0 | 0 | 0 | 0 |
Shift Register Empty Interrupt Flag
| Value | Name | Description |
|---|---|---|
| x | Slave | This bit is ignored |
| 1 | Master | The data transfer is complete |
| 0 | Master | Either no data transfers have occurred or a data transfer is in progress |
Transfer Counter is Zero Interrupt Flag
| Value | Description |
|---|---|
| 1 | The transfer counter has decremented to zero |
| 0 | No interrupt pending |
Start of Slave Select Interrupt Flag
| Value | Description |
|---|---|
| 1 | SS_in transitioned from false to true |
| 0 | No interrupt pending |
End of Slave Select Interrupt Flag
| Value | Description |
|---|---|
| 1 | SS_in transitioned from true to false |
| 0 | No interrupt pending |
Receiver Overflow Interrupt Flag
| Value | Description |
|---|---|
| 1 | Data
transfer completed when RXBF = 1 (edge-triggered) and RXR =
1 |
| 0 | No interrupt pending |
Transmitter Underflow Interrupt Flag
| Value | Description |
|---|---|
| 1 | Slave
Data transfer started when TXBE = 1 and TXR =
1 |
| 0 | No interrupt pending |