IPR3
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TMR0IP | CCP1IP | TMR1GIP | TMR1IP | TMR2IP | SPI1IP | SPI1TXIP | SPI1RXIP |
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
TMR0 Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
CCP1 Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
TMR1 Gate Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
TMR1 Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
TMR2 Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
SPI1 Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
SPI1 Transmit Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
SPI1 Receive Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |