IPR12
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DMA5AIP | DMA5ORIP | DMA5DCNTIP | DMA5SCNTIP | U4IP | U4EIP | U4TXIP | U4RXIP |
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
DMA5 Abort Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
DMA5 Overrun Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
DMA5 Destination Count Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
DMA5 Source Count Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
UART 4 Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
UART4 Framing Error Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
UART4 Transmit Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |
UART4 Receive Interrupt Priority
| Value | Description |
|---|---|
| 1 | High Priority |
| 0 | Low Priority |