Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the PPS Input Selection Table below).
Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.
| Peripheral | PPS Input Register | Default Pin Selection at POR | Register Reset Value at POR | Available Input Port | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 28-Pin Devices | 40-Pin Devices | 48-Pin Devices | |||||||||||||||
| Interrupt 0 | INT0PPS | RB0 | 'b001 000 |
A | B | — | A | B | — | — | — | A | B | — | — | — | — |
| Interrupt 1 | INT1PPS | RB1 | 'b001 001 |
A | B | — | A | B | — | — | — | — | B | — | D | — | — |
| Interrupt 2 | INT2PPS | RB2 | 'b001 010 |
A | B | — | A | B | — | — | — | — | B | — | — | — | F |
| Timer0 Clock | T0CKIPPS | RA4 | 'b000 100 |
A | B | — | A | B | — | — | — | A | — | — | — | — | F |
| Timer1 Clock | T1CKIPPS | RC0 | 'b010 000 |
A | — | C | A | — | C | — | — | — | — | C | — | E | — |
| Timer1 Gate | T1GPPS | RB5 | 'b001 101 |
— | B | C | — | B | C | — | — | — | B | C | — | — | — |
| Timer3 Clock | T3CKIPPS | RC0 | 'b010 000 |
— | B | C | — | B | C | — | — | — | — | C | — | E | — |
| Timer3 Gate | T3GPPS | RC0 | 'b010 000 |
A | — | C | A | — | C | — | — | A | — | C | — | — | — |
| Timer5 Clock | T5CKIPPS | RC2 | 'b010 010 |
A | — | C | A | — | C | — | — | — | — | C | — | E | — |
| Timer5 Gate | T5GPPS | RB4 | 'b001 100 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| Timer2 Input | T2INPPS | RC3 | 'b010 011 |
A | — | C | A | — | C | — | — | A | — | C | — | — | — |
| Timer4 Input | T4INPPS | RC5 | 'b010 101 |
— | B | C | — | B | C | — | — | — | B | C | — | — | — |
| Timer6 Input | T6INPPS | RB7 | 'b001 111 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| CCP1 | CCP1PPS | RC2 | 'b010 010 |
— | B | C | — | B | C | — | — | — | — | C | — | — | F |
| CCP2 | CCP2PPS | RC1 | 'b010 001 |
— | B | C | — | B | C | — | — | — | — | C | — | — | F |
| CCP3 | CCP3PPS | RB5 | 'b001 101 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| SMT1 Window | SMT1WINPPS | RC0 | 'b010 000 |
— | B | C | — | B | C | — | — | — | — | C | — | — | F |
| SMT1 Signal | SMT1SIGPPS | RC1 | 'b010 001 |
— | B | C | — | B | C | — | — | — | — | C | — | — | F |
| PWM Input 0 | PWMIN0PPS | RC2 | 'b010 010 |
— | B | C | — | B | C | — | — | — | — | C | — | — | F |
| PWM Input 1 | PWMIN1PPS | RC6 | 'b010 110 |
A | — | C | A | — | — | — | E | A | — | — | — | E | — |
| PWM1 External Reset Source | PWM1ERSPPS | RC3 | 'b010 011 |
A | — | C | A | — | C | — | — | A | — | C | — | — | |
| PWM2 External Reset Source | PWM2ERSPPS | RC5 | 'b010 101 |
A | — | C | A | — | C | — | — | — | — | C | — | E | — |
| PWM3 External Reset Source | PWM3ERSPPS | RB7 | 'b001 111 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| CWG1 | CWG1PPS | RB0 | 'b001 000 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| CWG2 | CWG2PPS | RB1 | 'b001 001 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| CWG3 | CWG3PPS | RB2 | 'b001 010 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| DSM1 Carrier Low | MD1CARLPPS | RA3 | 'b000 011 |
A | — | C | A | — | — | D | — | A | — | — | D | — | — |
| DSM1 Carrier High | MD1CARHPPS | RA4 | 'b000 100 |
A | — | C | A | — | — | D | — | A | — | — | D | — | — |
| DSM1 Source | MD1SRCPPS | RA5 | 'b000 101 |
A | — | C | A | — | — | D | — | A | — | — | D | — | — |
| CLCx Input 1 | CLCIN0PPS | RA0 | 'b000 000 |
A | — | C | A | — | C | — | — | A | — | C | — | — | — |
| CLCx Input 2 | CLCIN1PPS | RA1 | 'b000 001 |
A | — | C | A | — | C | — | — | A | — | C | — | — | — |
| CLCx Input 3 | CLCIN2PPS | RB6 | 'b001 110 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| CLCx Input 4 | CLCIN3PPS | RB7 | 'b001 111 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| CLCx Input 5 | CLCIN4PPS | RA0 | 'b000 000 |
A | — | C | A | — | C | — | — | A | — | C | — | — | — |
| CLCx Input 6 | CLCIN5PPS | RA1 | 'b000 001 |
A | — | C | A | — | C | — | — | A | — | C | — | — | — |
| CLCx Input 7 | CLCIN6PPS | RB6 | 'b001 110 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| CLCx Input 8 | CLCIN7PPS | RB7 | 'b001 111 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| ADC Conversion Trigger | ADACTPPS | RB4 | 'b001 100 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| SPI1 Clock | SPI1SCKPPS | RC3 | 'b010 011 |
— | B | C | — | B | C | — | — | — | B | C | — | — | — |
| SPI1 Data | SPI1SDIPPS | RC4 | 'b010 100 |
— | B | C | — | B | C | — | — | — | B | C | — | — | — |
| SPI1 Slave Select | SPI1SSPPS | RA5 | 'b000 101 |
A | — | C | A | — | — | D | — | A | — | — | D | — | — |
| SPI2 Clock | SPI2SCKPPS | RB3 | 'b001 011 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| SPI2 Data | SPI2SDIPPS | RB2 | 'b001 010 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| SPI2 Slave Select | SPI2SSPPS | RA4 | 'b000 100 |
A | — | C | A | — | — | D | — | A | — | — | D | — | — |
| I2C1 Clock | I2C1SCLPPS(1) | RC3 | 'b010 011 |
— | B | C | — | B | C | — | — | — | B | C | — | — | — |
| I2C1 Data | I2C1SDAPPS(1) | RC4 | 'b010 100 |
— | B | C | — | B | C | — | — | — | B | C | — | — | — |
| UART1 Receive | U1RXPPS | RC7 | 'b010 111 |
— | B | C | — | B | C | — | — | — | — | C | — | — | F |
| UART1 Clear to Send | U1CTSPPS | RC6 | 'b010 110 |
— | B | C | — | B | C | — | — | — | — | C | — | — | F |
| UART2 Receive | U2RXPPS | RB7 | 'b001 111 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| UART2 Clear to Send | U2CTSPPS | RB6 | 'b001 110 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| UART3 Receive | U3RXPPS | RA7 | 'b000 111 |
A | B | — | A | B | — | — | — | A | — | — | — | — | F |
| UART3 Clear to Send | U3CTSPPS | RA6 | 'b000 110 |
A | B | — | A | B | — | — | — | A | — | — | — | — | F |
| UART4 Receive | U4RXPPS | RB5 | 'b001 101 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| UART4 Clear to Send | U4CTSPPS | RB4 | 'b001 100 |
— | B | C | — | B | — | D | — | — | B | — | D | — | — |
| UART5 Receive | U5RXPPS | RA5 | 'b000 101 |
A | — | C | A | — | C | — | — | A | — | — | — | — | F |
| UART5 Clear to Send | U5CTSPPS | RA4 | 'b000 100 |
A | — | C | A | — | C | — | — | A | — | — | — | — | F |