SMTxCON0

SMTxCON0

SMT Control Register 0

Name:: SMTxCON0
Address:: 0x030C
Reset:
Access:

Bit7	6	5	4	3	2	1	0
EN		STP	WPOL	SPOL	CPOL	PS[1:0]
AccessR/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset0		0	0	0	0	0	0

Bit 7 – EN: SMT Enable

SMT Enable

Value	Description
`1`	SMT is enabled
`0`	SMT is disabled; internal states are reset, clock requests are disabled

Bit 5 – STP: SMT Counter Halt Enable

SMT Counter Halt Enable

Value	Name	Description
`1`	When SMTxTMR = SMTxPR	Counter remains at SMTxPR; period match interrupt occurs when clocked
`0`	When SMTxTMR = SMTxPR	Counter resets to 0x000000; period match interrupt occurs when clocked

Bit 4 – WPOL: SMT_window Input Polarity Control

SMT_window Input Polarity Control

Value	Description
`1`	SMT_window input is active-low/falling edge enabled
`0`	SMT_window input is active-high/rising edge enabled

Bit 3 – SPOL: SMT_signal Input Polarity Control

SMT_signal Input Polarity Control

Value	Description
`1`	SMT_signal input is active-low/falling edge enabled
`0`	SMT_signal input is active-high/rising edge enabled

Bit 2 – CPOL: SMT Clock Input Polarity Control

SMT Clock Input Polarity Control

Value	Description
`1`	SMTxTMR increments on the falling edge of the selected clock signal
`0`	SMTxTMR increments on the rising edge of the selected clock signal

Bits 1:0 – PS[1:0]: SMT Prescale Select

SMT Prescale Select

Value	Description
11	Prescaler = 1:8
10	Prescaler = 1:4
01	Prescaler = 1:2
00	Prescaler = 1:1