UxP3
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| P3[8] | |||||||
| Access | R/W | ||||||
| Reset | 0 | ||||||
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| P3[7:0] | |||||||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Parameter 3 Most Significant bit
| Value | Name | Description |
|---|---|---|
| n | MODE = DMX | Most Significant bit of last address of receive block |
| x | All other modes/Limited featured UART | Not used |
Parameter 3 Least Significant bits
| Value | Name | Description |
|---|---|---|
| n | MODE = DMX | Least Significant bits of last address of receive block |
| n | MODE = LIN Slave | Number of data bytes to receive |
| n | MODE = Asynchronous Address | Receiver address mask. Received address is XOR’d with UxP2L then AND’d with UxP3L Match occurs when result is zero |
| x | All other modes | Not used |