When the peripheral priority (e.g., DMA, Scanner) is lower than ISR and MAIN
priority, and the peripheral requires:
- 1.Access to the Program Flash
Memory, then the peripheral waits for an instruction cycle in which the CPU does
not need to access the PFM (such as a branch instruction) and uses that cycle to
do its own Program Flash Memory access, unless a PFM Read/Write operation is in
progress.
- 2.Access to the SFR/GPR, then the
peripheral waits for an instruction cycle in which the CPU does not need to
access the SFR/GPR (such as
MOVLW, CALL,
NOP) and uses that cycle to do its own SFR/GPR access.
- 3.Access to the Data EEPROM, then
the peripheral has access to Data EEPROM unless a Data EEPROM Read/Write
operation is being performed.
This results in the lowest throughput for the peripheral to access the memory, and does
so without any impact on execution times.