PIR2

Peripheral Interrupt Request Register 2
Note:
  1. 1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
Name:
PIR2
Address:
0x4B0
Reset:
Access:
Bit76543210
DMA1AIFDMA1ORIFDMA1DCNTIFDMA1SCNTIFADTIF
AccessR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS
Reset00000

Bit 7 – DMA1AIF: DMA1 Abort Interrupt Flag

DMA1 Abort Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 6 – DMA1ORIF: DMA1 Overrun Interrupt Flag

DMA1 Overrun Interrupt Flag

ValueDescription
0 Interrupt event has not occurred
1 Interrupt has occurred

Bit 5 – DMA1DCNTIF: DMA1 Destination Count Interrupt Flag

DMA1 Destination Count Interrupt Flag

ValueDescription
0 Interrupt event has not occurred
1 Interrupt has occurred

Bit 4 – DMA1SCNTIF: DMA1 Source Count Interrupt Flag

DMA1 Source Count Interrupt Flag

ValueDescription
0 Interrupt event has not occurred
1 Interrupt has occurred

Bit 0 – ADTIF: ADC Threshold Interrupt Flag

ADC Threshold Interrupt Flag

ValueDescription
0 Interrupt event has not occurred
1 Interrupt has occurred