PIR5

Peripheral Interrupt Request Register 5
Note:
  1. 1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
  2. 2.PWM2IF is a read-only bit. To clear the interrupt condition, all bits in the PWM2GIR register must be cleared.
  3. 3.SPI2IF is a read-only bit. TO clear the interrupt condition, all bits in the SPI2INTF register must be cleared.
  4. 4.SPI2TXIF and SPI2RXIF are read-only bits and cannot be set/cleared by software.
Name:
PIR5
Address:
0x4B3
Reset:
Access:
Bit76543210
PWM2IFPWM2PIFTMR3GIFTMR3IFSPI2IFSPI2TXIFSPI2RXIF
AccessRR/W/HSR/W/HSR/W/HSRRR
Reset0000000

Bit 7 – PWM2IF: PWM2 Parameter Interrupt Flag(2)

PWM2 Parameter Interrupt Flag(2)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 6 – PWM2PIF: PWM2 Period Interrupt Flag

PWM2 Period Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 5 – TMR3GIF: TMR3 Gate Interrupt Flag

TMR3 Gate Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 4 – TMR3IF: TMR3 Interrupt Flag

TMR3 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 2 – SPI2IF: SPI2 Interrupt Flag(3)

SPI2 Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 1 – SPI2TXIF: SPI2 Transmit Interrupt Flag(4)

SPI2 Transmit Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 0 – SPI2RXIF: SPI2 Receive Interrupt Flag(4)

SPI2 Receive Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred