PIR10

Peripheral Interrupt Request Register 10
Note:
  1. 1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
Name:
PIR10
Address:
0x4B8
Reset:
Access:
Bit76543210
DMA3AIFDMA3ORIFDMA3DCNTIFDMA3SCNTIFNCO2IFCWG2IFCLC5IFINT2IF
AccessR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS
Reset00000000

Bit 7 – DMA3AIF: DMA3 Abort Interrupt Flag

DMA3 Abort Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 6 – DMA3ORIF: DMA3 Overrun Interrupt Flag

DMA3 Overrun Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 5 – DMA3DCNTIF: DMA3 Destination Count Interrupt Flag

DMA3 Destination Count Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 4 – DMA3SCNTIF: DMA3 Source Count Interrupt Flag

DMA3 Source Count Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 3 – NCO2IF: NCO2 Interrupt Flag

NCO2 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 2 – CWG2IF: CWG2 Interrupt Flag

CWG2 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 1 – CLC5IF: CLC5 Interrupt Flag

CLC5 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 0 – INT2IF: External Interrupt 2 Interrupt Flag

External Interrupt 2 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred