The Doze operation is illustrated in Figure 1. As with normal operation, the instruction is fetched for the next instruction cycle while the previous instruction is executed. The Q-clocks to the peripherals continue throughout the periods in which no instructions are fetched or executed. The following configuration settings apply for this example:
- Doze enabled (DOZEN =
1) - CPU instruction cycle to peripheral instruction cycle ratio of 1:4
- Recover-on-Interrupt enabled (ROI =
1)
Figure 1. Doze Mode Operation Example
Note:
- 1.Multicycle instructions are executed
to completion before fetching
0x0004. - 2.If the prefetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed.