PIR8

Peripheral Interrupt Request Register 8

Note:

1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
2.U2IF is a read-only bit. To clear the interrupt condition, all bits in the U2UIR register must be cleared.
3.U2EIF is a read-only bit. To clear the interrupt condition, all bits in the U2ERR register must be cleared.
4.U2TXIF and U2RXIF are read-only bits and cannot be set/cleared by software.

Bit 7 – SCANIF: Memory Scanner Interrupt Flag

Memory Scanner Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 6 – CCP2IF: CCP2 Interrupt Flag

CCP2 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 5 – TMR5GIF: TMR5 Gate Interrupt Flag

TMR5 Gate Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 4 – TMR5IF: TMR5 Interrupt Flag

TMR5 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 3 – U2IF: UART2 Interrupt Flag(2)

UART2 Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 2 – U2EIF: UART2 Framing Error Interrupt Flag(3)

UART2 Framing Error Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 1 – U2TXIF: UART2 Transmit Interrupt Flag(4)

UART2 Transmit Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 0 – U2RXIF: UART2 Receive Interrupt Flag(4)

UART2 Receive Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred