TxCLK

TxCLK

Timer Clock Source Selection Register

Name:: TxCLK
Address:: 0x321,0x32D,0x339
Reset:
Access:

Bit7	6	5	4	3	2	1	0
			CS[4:0]
Access			R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0

Bits 4:0 – CS[4:0]: Timer Clock Source Selection

Timer Clock Source Selection

Table 1. Timer Clock Sources
CS	Clock Source
CS	Timer1	Timer3	Timer5
`11111-10110`	Reserved
`10101`	CLC8_OUT
`10100`	CLC7_OUT
`10011`	CLC6_OUT
`10010`	CLC5_OUT
`10001`	CLC4_OUT
`10000`	CLC3_OUT
`01111`	CLC2_OUT
`01110`	CLC1_OUT
`01101`	TMR5_OUT	TMR5_OUT	Reserved
`01100`	TMR3_OUT	Reserved	TMR3_OUT
`01011`	Reserved	TMR1_OUT	TMR1_OUT
`01010`	TMR0_OUT
`01001`	CLKREF_OUT
`01000`	EXTOSC
`00111`	SOSC
`00110`	MFINTOSC (31.25 kHz)
`00101`	MFINTOSC (500 kHz)
`00100`	LFINTOSC
`00011`	HFINTOSC
`00010`	F_OSC
`00001`	F_OSC/4
`00000`	Pin selected by T1CKIPPS	Pin selected by T3CKIPPS	Pin selected by T5CKIPPS