To write a DFM location, the address must first be written to the NVMADR register, the data written to the NVMDATL register, and the Write operation command set in the NVMCMD bits. The sequence shown in Unlock Sequence must be followed to initiate the write cycle. Multi-byte Page writes are not supported for the DFM.
The write will not begin if the NVM unlock sequence is not exactly followed for each byte. It is strongly recommended that interrupts be disabled during this code segment.
When not actively writing to the DFM, the NVMCMD bits should be kept clear at all times as an extra precaution against accidental writes. The NVMCMD bits are not cleared by hardware.
After a write sequence has been initiated, NVMCON0, NVMCON1, NVMADR and NVMDAT cannot be modified.
Each DFM write operation includes an implicit erase cycle for that byte. CPU execution continues in parallel and at the completion of the write cycle, the GO bit is cleared in hardware and the NVM Interrupt Flag bit (NVMIF) is set. The user can either enable the interrupt or poll the bit. NVMIF must be cleared by software.
; Data Flash Memory Address to write
MOVF DFM_ADDRL, W
MOVWF NVMADRL ; Setup Address low byte
MOVF DFM_ADDRH, W
MOVWF NVMADRH ; Setup Address high byte
MOVF DFM_ADDRU, W ;
MOVWF NVMADRU ; Setup Address upper byte
; Data Memory Value to write
MOVF DMF_DATA, W
MOVWF NVMDATL
; Enable writes
MOVLW 0x03 ; write command (use 0x04 for NVMADR++)
MOVWF NVMCON1
; Disable interrupts
BCF INTCON0, GIE
; –------- Required Sequence –--------
MOVLW 0x55
MOVWF NVMLOCK
MOVLW 0xAA
MOVWF NVMLOCK
BSF NVMCON0, GO ; Set GO bit to begin write
; –------------------------------------
; Wait for write to complete
BTFSC NVMCON0, GO ; DFM writes do not stall the CPU
BRA $-2
; Enable Interrupts (optional)
BSF INTCON0, GIE
; Disable writes
CLRF NVMCON1