PIR13

Peripheral Interrupt Request Register 13

Note:

1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
2.U5IF is a read-only bit. To clear the interrupt condition, all bits in the U5UIR register must be cleared.
3.U5EIF is a read-only bit. To clear the interrupt condition, all bits in the U5ERR register must be cleared.
4.U5TXIF and U5RXIF are read-only bits and cannot be set/cleared by software.

Bit 7 – DMA6AIF: DMA6 Abort Interrupt Flag

DMA6 Abort Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 6 – DMA6ORIF: DMA6 Overrun Interrupt Flag

DMA6 Overrun Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 5 – DMA6DCNTIF: DMA6 Destination Count Interrupt Flag

DMA6 Destination Count Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 4 – DMA6SCNTIF: DMA6 Source Count Interrupt Flag

DMA6 Source Count Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 3 – U5IF: UART5 Interrupt Flag(2)

UART5 Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 2 – U5EIF: UART5 Framing Error Interrupt Flag(3)

UART5 Framing Error Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 1 – U5TXIF: UART5 Transmit Interrupt Flag(4)

UART5 Transmit Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 0 – U5RXIF: UART5 Receive Interrupt Flag(4)

UART5 Receive Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred