PIR4

Peripheral Interrupt Request Register 4
Note:
  1. 1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
  2. 2.PWM1IF is a read-only bit. To clear the interrupt condition, all bits in the PWM1GIR register must be cleared.
  3. 3.U1IF is a read-only bit. To clear the interrupt condition, all bits in the U1UIR register must be cleared.
  4. 4.U1EIF is a read-only bit. To clear the interrupt condition, all bits in the U1ERR register must be cleared.
  5. 5.U1TXIF and U1RXIF are read-only bits and cannot be set/cleared by software.
Name:
PIR4
Address:
0x4B2
Reset:
Access:
Bit76543210
PWM1IFPWM1PIFU1IFU1EIFU1TXIFU1RXIF
AccessRR/W/HSRRRR
Reset000000

Bit 7 – PWM1IF: PWM1 Parameter Interrupt Flag(2)

PWM1 Parameter Interrupt Flag(2)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 6 – PWM1PIF: PWM1 Period Interrupt Flag

PWM1 Period Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 3 – U1IF: UART1 Interrupt Flag(3)

UART1 Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 2 – U1EIF: UART1 Framing Error Interrupt Flag(4)

UART1 Framing Error Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 1 – U1TXIF: UART1 Transmit Interrupt Flag(5)

UART1 Transmit Interrupt Flag(5)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 0 – U1RXIF: UART 1 Receive Interrupt Flag(5)

UART 1 Receive Interrupt Flag(5)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred