SPIxCON2

Note:
  1. 1.The BUSY bit is subject to synchronization delay of up to two instruction cycles. The user must wait after loading the transmit buffer (SPIxTXB register) before using it to determine the status of the SPI module.
  2. 2.See Master Mode TXR/RXR Settings table as well as section Master Mode and section Slave Mode for more details pertaining to TXR and RXR function.
  3. 3.This register should not be written to while a transfer is in progress (BUSY bit is set).
Name:
SPIxCON2
Address:
0x086,0x093
Reset:
Access:
Bit76543210
BUSYSSFLTSSETTXRRXR
AccessRRR/WR/WR/W
Reset00000

Bit 7 – BUSY: SPI Module Busy Status(1)

SPI Module Busy Status(1)

ValueDescription
1 Data exchange is busy
0 Data exchange is not taking place

Bit 6 – SSFLT: SS_in Fault Status

SS_in Fault Status

ValueNameDescription
x SSET = 1 This bit is unchanged
1 SSET = 0 SS_in ended the transaction unexpectedly, and the data byte being received was lost
0 SSET = 0 SS_in ended normally

Bit 2 – SSET: Slave Select Enable

Slave Select Enable

ValueNameDescription
1 Master SS_out is driven to the Active state continuously
0 Master SS_out is driven to the Active state while the transmit counter is not zero
1 Slave SS_in is ignored and data is clocked on all SCK_in (as though SS = TRUE at all times)
0 Slave SS_in enables/disables data input and tri-states SDO if the TRIS bit associated with the SDO pin is set (see Slave Mode Transmit table for details)

Bit 1 – TXR: Transmit Data-Required Control(2)

Transmit Data-Required Control(2)

ValueDescription
1 TxFIFO data is required for a transfer
0 TxFIFO data is not required for a transfer

Bit 0 – RXR: Receive FIFO Space-Required Control(2)

Receive FIFO Space-Required Control(2)

ValueDescription
1 Data transfers are suspended when the RxFIFO is full
0 Received data is not stored in the FIFO