In this mode, either the duty cycle or period of the input signal can be acquired relative to the SMT clock. The SMTxCPW register is updated on a falling edge of the signal, and the SMTxCPR register is updated on a rising edge of the signal. The rising edge also resets the SMTxTMR register to 0x000001. The GO bit is reset on a rising edge when the SMT is in Single Acquisition mode. Refer to the figures below.
Figure 1. Period and Duty Cycle, Repeat
Acquisition Mode Timing Diagram
Figure 2. Period and Duty Cycle, Single
Acquisition Mode Timing Diagram
