PIR9

Peripheral Interrupt Request Register 9
Note:
  1. 1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
  2. 2.U3IF is a read-only bit. To clear the interrupt condition, all bits in the U3UIR register must be cleared.
  3. 3.U3EIF is a read-only bit. To clear the interrupt condition, all bits in the U3ERR register must be cleared.
  4. 4.U3TXIF and U3RXIF are read-only bits and cannot be set/cleared by software.
Name:
PIR9
Address:
0x4B7
Reset:
Access:
Bit76543210
CLC4IFU3IFU3EIFU3TXIFU3RXIF
AccessR/W/HSRRRR
Reset00000

Bit 5 – CLC4IF: CLC4 Interrupt Flag

CLC4 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 3 – U3IF: UART3 Interrupt Flag(2)

UART3 Interrupt Flag(2)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 2 – U3EIF: UART3 Framing Error Interrupt Flag(3)

UART3 Framing Error Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 1 – U3TXIF: UART3 Transmit Interrupt Flag(4)

UART3 Transmit Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 0 – U3RXIF: UART3 Receive Interrupt Flag(4)

UART3 Receive Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred