Contents

Introduction PIC18-Q43 Family Types Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Q43 Block Diagram 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables 4. Guidelines for Getting Started with PIC18-Q43 Microcontrollers 4.1. Basic Connection Requirements 4.2. Power Supply Pins 4.2.1. Decoupling Capacitors 4.2.2. Tank Capacitors 4.3. Master Clear (MCLR) Pin 4.4. In-Circuit Serial Programming (ICSP) Pins 4.5. External Oscillator Pins 4.6. Unused I/Os 5. Register and Bit Naming Conventions 5.1. Register Names 5.2. Bit Names 5.2.1. Short Bit Names 5.2.2. Long Bit Names 5.2.3. Bit Fields 5.3. Register and Bit Naming Exceptions 5.3.1. Status, Interrupt, and Mirror Bits 6. Register Legend 7. PIC18 CPU 7.1. System Arbitration 7.1.1. Priority Lock 7.2. Memory Access Scheme 7.2.1. ISR Priority > Main Priority > Peripheral Priority 7.2.2. Peripheral Priority > ISR Priority > Main Priority 7.2.3. ISR Priority > Peripheral Priority > Main Priority 7.2.4. Peripheral 1 Priority > ISR Priority > Main Priority > Peripheral 2 Priority 7.3. 8x8 Hardware Multiplier 7.3.1. Operation 7.3.2. 16x16 Unsigned Multiplication Algorithm 7.3.3. 16x16 Signed Multiplication Algorithm 7.4. PIC18 Instruction Cycle 7.4.1. Instruction Flow/Pipelining 7.4.2. Instructions in Program Memory 7.4.3. Multi-Word Instructions 7.5. STATUS Register 7.6. Call Shadow Register 7.7. Register Definitions: System Arbiter 7.7.1. ISRPR 7.7.2. MAINPR 7.7.3. DMAxPR 7.7.4. SCANPR 7.7.5. PRLOCK 7.7.6. PROD 7.7.7. STATUS 7.8. Register Summary - System Arbiter Control 8. Device Configuration 8.1. Configuration Settings 8.2. Code Protection 8.3. User ID 8.4. Device ID and Revision ID 8.5. Register Definitions: Configuration Settings 8.5.1. CONFIG1 8.5.2. CONFIG2 8.5.3. CONFIG3 8.5.4. CONFIG4 8.5.5. CONFIG5 8.5.6. CONFIG6 8.5.7. CONFIG7 8.5.8. CONFIG8 8.5.9. CONFIG9 8.5.10. CONFIG10 8.6. Register Summary - Configuration Settings 8.7. Register Definitions: Device ID and Revision ID 8.7.1. Device ID 8.7.2. Revision ID 8.8. Register Summary - DEVID/REVID 9. Memory Organization 9.1. Program Memory Organization 9.1.1. Memory Access Partition 9.1.1.1. Application Block 9.1.1.2. Boot Block 9.1.1.3. Storage Area Flash 9.1.2. Program Counter 9.1.3. Return Address Stack 9.1.3.1. Top-of-Stack Access 9.1.3.2. Return Stack Pointer 9.1.3.3. PUSH and POP Instructions 9.1.3.4. Fast Register Stack 9.1.4. Look-up Tables in Program Memory 9.1.4.1. Computed GOTO 9.1.4.2. Program Flash Memory Access 9.2. Device Information Area 9.2.1. Microchip Unique Identifier (MUI) 9.2.2. External Unique Identifier (EUI) 9.2.3. Standard Parameters for the Temperature Sensor 9.2.4. Fixed Voltage Reference Data 9.3. Device Configuration Information 9.4. Data Memory Organization 9.4.1. Bank Select Register 9.4.2. Access Bank 9.5. Data Addressing Modes 9.5.1. Inherent and Literal Addressing 9.5.2. Direct Addressing 9.5.3. Indirect Addressing 9.5.3.1. FSR Registers and the INDF Operand 9.5.3.2. FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW 9.5.3.3. Operations by FSRs on FSRs 9.6. Data Memory and the Extended Instruction Set 9.6.1. Indexed Addressing with Literal Offset 9.6.2. Instructions Affected by Indexed Literal Offset Mode 9.6.3. Mapping the Access Bank in Indexed Literal Offset Mode 9.6.4. PIC18 Instruction Execution and the Extended Instruction Set 9.7. Register Definitions: Memory Organization 9.7.1. PCL 9.7.2. PCLAT 9.7.3. TOS 9.7.4. STKPTR 9.7.5. WREG 9.7.6. INDFx 9.7.7. POSTDECx 9.7.8. POSTINCx 9.7.9. PREINCx 9.7.10. PLUSWx 9.7.11. FSRx 9.7.12. BSR 9.8. Register Summary - Memory Organization 10. NVM - Nonvolatile Memory Module 10.1. PFM - Program Flash Memory 10.1.1. Operations 10.1.2. Table Pointer Operations 10.1.2.1. Table Pointer Register 10.1.2.2. Table Latch Register 10.1.2.3. Table Read Operations 10.1.2.4. Table Write Operations 10.1.2.5. Table Pointer Boundaries 10.1.2.6. Reading the Program Flash Memory 10.1.3. Page Operations 10.1.4. Unlock Sequence 10.1.5. Erasing Program Flash Memory (PFM) 10.1.5.1. PFM Erase Sequence 10.1.6. Writing to Program Flash Memory 10.1.6.1. PFM Page Write Sequence 10.1.6.2. PFM Word Write Sequence 10.1.6.3. Write Verify 10.1.6.4. Unexpected Termination of Write Operation 10.1.7. User ID, Device ID, Configuration Settings Access, DIA and DCI 10.2. Data Flash Memory (DFM) 10.2.1. Reading the DFM 10.2.2. Writing to DFM 10.2.3. DFM Write Verify 10.2.4. Operation During Code-Protect and Write-Protect 10.2.5. Protection Against Spurious Writes 10.2.6. Erasing the DFM 10.3. Register Definitions: NVM 10.3.1. NVMCON0 10.3.2. NVMCON1 10.3.3. NVMLOCK 10.3.4. NVMADR 10.3.5. NVMDAT 10.3.6. TBLPTR 10.3.7. TABLAT 10.4. Register Summary - NVM 11. VIC - Vectored Interrupt Controller Module 11.1. Overview 11.2. Interrupt Control and Status Registers 11.3. Interrupt Vector Table 11.3.1. Interrupt Vector Table Base Address (IVTBASE) 11.3.2. Interrupt Vector Table Contents 11.3.3. Interrupt Vector Table Address Calculation 11.3.4. Access Control for IVTBASE Registers 11.4. Interrupt Priority 11.4.1. User (Software) Priority 11.4.2. Natural Order (Hardware) Priority 11.5. Interrupt Operation 11.5.1. Serving a High- or Low-Priority Interrupt while the Main Routine Code is Executing 11.5.2. Serving a High-Priority Interrupt while a Low-Priority Interrupt is Pending 11.5.3. Preempting Low-Priority Interrupts 11.5.4. Simultaneous High- and Low-Priority Interrupts 11.6. Context Saving 11.6.1. Accessing Shadow Registers 11.7. Returning from Interrupt Service Routine (ISR) 11.8. Interrupt Latency 11.8.1. Aborting Interrupts 11.9. Interrupt Setup Procedure 11.10. External Interrupt Pins 11.11. Wake-up from Sleep 11.12. Interrupt Compatibility 11.13. Register Definitions: Interrupt Control 11.13.1. INTCON0 11.13.2. INTCON1 11.13.3. IVTBASE 11.13.4. IVTAD 11.13.5. IVTLOCK 11.13.6. SHADCON 11.13.7. PIE0 11.13.8. PIE1 11.13.9. PIE2 11.13.10. PIE3 11.13.11. PIE4 11.13.12. PIE5 11.13.13. PIE6 11.13.14. PIE7 11.13.15. PIE8 11.13.16. PIE9 11.13.17. PIE10 11.13.18. PIE11 11.13.19. PIE12 11.13.20. PIE13 11.13.21. PIE14 11.13.22. PIE15 11.13.23. PIR0 11.13.24. PIR1 11.13.25. PIR2 11.13.26. PIR3 11.13.27. PIR4 11.13.28. PIR5 11.13.29. PIR6 11.13.30. PIR7 11.13.31. PIR8 11.13.32. PIR9 11.13.33. PIR10 11.13.34. PIR11 11.13.35. PIR12 11.13.36. PIR13 11.13.37. PIR14 11.13.38. PIR15 11.13.39. IPR0 11.13.40. IPR1 11.13.41. IPR2 11.13.42. IPR3 11.13.43. IPR4 11.13.44. IPR5 11.13.45. IPR6 11.13.46. IPR7 11.13.47. IPR8 11.13.48. IPR9 11.13.49. IPR10 11.13.50. IPR11 11.13.51. IPR12 11.13.52. IPR13 11.13.53. IPR14 11.13.54. IPR15 11.14. Register Summary - Interrupts 12. OSC - Oscillator Module (With Fail-Safe Clock Monitor) 12.1. Clock Source Types 12.1.1. External Clock Sources 12.1.1.1. EC Mode 12.1.1.2. LP, XT, HS Modes 12.1.1.3. Oscillator Start-Up Timer (OST) 12.1.1.4. 4x PLL 12.1.1.5. Secondary Oscillator 12.1.1.5.1. SOSC Start-Up Timing 12.1.2. Internal Clock Sources 12.1.2.1. HFINTOSC 12.1.2.1.1. HFINTOSC Frequency Tuning 12.1.2.2. MFINTOSC 12.1.2.3. LFINTOSC 12.1.2.4. ADCRC 12.1.3. Oscillator Status and Manual Enable 12.2. Clock Switching 12.2.1. NOSC and NDIV Bits 12.2.2. COSC and CDIV Bits 12.2.3. CSWHOLD 12.2.4. PLL Input Switch 12.2.5. Clock Switch and Sleep 12.3. Fail-Safe Clock Monitor (FSCM) 12.3.1. Fail-Safe Detection 12.3.2. Fail-Safe Operation 12.3.3. Fail-Safe Condition Clearing 12.3.4. Reset or Wake-Up From Sleep 12.4. Active Clock Tuning (ACT) 12.4.1. ACT Lock Status 12.4.2. ACT Out-Of-Range Status 12.4.3. ACT Update Disable 12.4.4. ACT Interrupts 12.5. Register Definitions: Oscillator Module 12.5.1. ACTCON 12.5.2. OSCCON1 12.5.3. OSCCON2 12.5.4. OSCCON3 12.5.5. OSCTUNE 12.5.6. OSCFRQ 12.5.7. OSCSTAT 12.5.8. OSCEN 12.6. Register Summary - Oscillator Module 13. CRC - Cyclic Redundancy Check Module with Memory Scanner 13.1. CRC Module Overview 13.2. CRC Functional Overview 13.3. CRC Polynomial Implementation 13.4. CRC Data Sources 13.4.1. CRC from User Data 13.4.2. CRC from Flash 13.5. CRC Check Value 13.6. CRC Interrupt 13.7. Configuring the CRC 13.8. Scanner Module Overview 13.9. Configuring the Scanner 13.10. Scanner Interrupt 13.11. Scanning Modes 13.11.1. TRIGEN = 0, BURSTMD = 0 13.11.2. TRIGEN = 1, BURSTMD = 0 13.11.3. TRIGEN = x, BURSTMD = 1 13.11.4. WWDT interaction 13.11.5. Peripheral Module Disable 13.12. Register Definitions: CRC and Scanner Control 13.12.1. CRCCON0 13.12.2. CRCCON1 13.12.3. CRCDATA 13.12.4. CRCACC 13.12.5. CRCSHIFT 13.12.6. CRCXOR 13.12.7. SCANCON0 13.12.8. SCANLADR 13.12.9. SCANHADR 13.12.10. SCANTRIG 13.13. Register Summary - CRC 14. Resets 14.1. Power-on Reset (POR) 14.2. Brown-out Reset (BOR) 14.2.1. BOR is Always ON 14.2.2. BOR is OFF in Sleep 14.2.3. BOR Controlled by Software 14.2.4. BOR is always OFF 14.2.5. BOR and Bulk Erase 14.3. Low-Power Brown-out Reset (LPBOR) 14.3.1. Enabling LPBOR 14.3.2. LPBOR Module Output 14.4. MCLR Reset 14.4.1. MCLR Enabled 14.4.2. MCLR Disabled 14.5. Windowed Watchdog Timer (WWDT) Reset 14.6. RESET Instruction 14.7. Stack Overflow/Underflow Reset 14.8. Programming Mode Exit 14.9. Power-up Timer (PWRT) 14.10. Start-up Sequence 14.10.1. Memory Execution Violation 14.11. Determining the Cause of a Reset 14.12. Power Control (PCON0/PCON1) Registers 14.13. Register Definitions: Power Control 14.13.1. BORCON 14.13.2. PCON0 14.13.3. PCON1 14.14. Register Summary - BOR Control and Power Control 15. WWDT - Windowed Watchdog Timer 15.1. Independent Clock Source 15.2. WWDT Operating Modes 15.2.1. WWDT Is Always On 15.2.2. WWDT is Off in Sleep 15.2.3. WWDT Controlled by Software 15.3. Time-out Period 15.4. Watchdog Window 15.5. Clearing the Watchdog Timer 15.5.1. CLRWDT Considerations (Windowed Mode) 15.6. Operation During Sleep 15.7. Register Definitions: Windowed Watchdog Timer Control 15.7.1. WDTCON0 15.7.2. WDTCON1 15.7.3. WDTPSH 15.7.4. WDTPSL 15.7.5. WDTTMR 15.8. Register Summary: WDT Control 16. DMA - Direct Memory Access 16.1. DMA Registers 16.2. DMA Organization 16.3. DMA Interface 16.3.1. Special Function Registers with DMA Access only 16.3.2. DMA Addressing 16.3.3. DMA Message Size/Counters 16.3.4. DMA Message Transfers 16.3.4.1. Starting DMA Message Transfers 16.3.4.1.1. User Software Control 16.3.4.1.2. Hardware Trigger, SIRQ 16.3.4.2. Stopping DMA Message Transfers 16.3.4.2.1. User Software Control 16.3.4.2.2. Hardware Trigger, AIRQ 16.3.4.2.3. Source Count Reload 16.3.4.2.4. Destination Count Reload 16.3.4.2.5. Clearing the EN bit 16.4. Disable DMA Message Transfer Upon Completion 16.4.1. Clearing the SIRQEN bit 16.4.2. Source/Destination Stop 16.5. Types of Hardware Triggers 16.5.1. Edge Trigger Requests 16.5.2. Level Trigger Requests 16.6. Types of Data Transfers 16.7. DMA Interrupts 16.7.1. DMA Source Count Interrupt 16.7.2. DMA Destination Count Interrupt 16.7.3. Abort Interrupt 16.7.4. Overrun Interrupt 16.8. DMA Setup and Operation 16.8.1. Source Stop 16.8.2. Destination Stop 16.8.3. Continuous Transfer 16.8.4. Transfer from SFR to GPR 16.8.5. Overrun Condition 16.8.6. Abort Trigger, Message Complete 16.8.7. Abort Trigger, Message in Progress 16.9. Reset 16.10. Power-Saving Mode Operation 16.10.1. Sleep Mode 16.10.2. Idle Mode 16.10.3. Doze Mode 16.10.4. Peripheral Module Disable 16.11. Example Setup Code 16.12. Register Overlay 16.13. Register Definitions: DMA 16.13.1. DMASELECT 16.13.2. DMAnCON0 16.13.3. DMAnCON1 16.13.4. DMAnBUF 16.13.5. DMAnSSA 16.13.6. DMAnSSZ 16.13.7. DMAnSCNT 16.13.8. DMAnSPTR 16.13.9. DMAnDSA 16.13.10. DMAnDSZ 16.13.11. DMAnDCNT 16.13.12. DMAnDPTR 16.13.13. DMAnSIRQ 16.13.14. DMAnAIRQ 16.14. Register Summary - DMA 17. Power-Saving Modes 17.1. Doze Mode 17.1.1. Doze Operation 17.1.2. Interrupts During Doze 17.2. Sleep Mode 17.2.1. Wake-up from Sleep 17.2.2. Wake-up Using Interrupts 17.2.3. Low-Power Sleep Mode 17.2.3.1. Sleep Current vs. Wake-up Time 17.2.3.2. Peripheral Usage in Sleep 17.3. Idle Mode 17.3.1. Idle and Interrupts 17.3.2. Idle and WWDT 17.4. Peripheral Operation in Power-Saving Modes 17.5. Register Definitions: Power-Savings Control 17.5.1. CPUDOZE 17.5.2. VREGCON 17.6. Register Summary - Power-Savings Control 18. PMD - Peripheral Module Disable 18.1. Overview 18.2. Disabling a Module 18.3. Enabling a Module 18.4. Register Definitions: Peripheral Module Disable 18.4.1. PMD0 18.4.2. PMD1 18.4.3. PMD3 18.4.4. PMD4 18.4.5. PMD5 18.4.6. PMD6 18.4.7. PMD7 18.4.8. PMD8 18.5. Register Summary - PMD 19. I/O Ports 19.1. Overview 19.2. PORTx - Data Register 19.3. LATx - Output Latch 19.4. TRISx - Direction Control 19.5. ANSELx - Analog Control 19.6. WPUx - Weak Pull-Up Control 19.7. INLVLx - Input Threshold Control 19.8. SLRCONx - Slew Rate Control 19.9. ODCONx - Open-Drain Control 19.10. Edge Selectable Interrupt-on-Change 19.11. I2C Pad Control 19.12. I/O Priorities 19.13. MCLR/VPP/RE3 Pin 19.14. Register Definitions: Port Control 19.14.1. PORTx 19.14.2. LATx 19.14.3. TRISx 19.14.4. ANSELx 19.14.5. WPUx 19.14.6. INLVLx 19.14.7. SLRCONx 19.14.8. ODCONx 19.14.9. RxyI2C 19.15. Register Summary - IO Ports 20. IOC - Interrupt-on-Change 20.1. Overview 20.2. Enabling the Module 20.3. Individual Pin Configuration 20.4. Interrupt Flags 20.5. Clearing Interrupt Flags 20.6. Operation in Sleep 20.7. Register Definitions: Interrupt-on-Change Control 20.7.1. IOCxF 20.7.2. IOCxN 20.7.3. IOCxP 20.8. Register Summary: Interrupt-on-Change Control 21. PPS - Peripheral Pin Select Module 21.1. Overview 21.2. PPS Inputs 21.3. PPS Outputs 21.4. Bidirectional Pins 21.5. PPS Lock 21.5.1. PPS One-Way Lock 21.6. Operation During Sleep 21.7. Effects of a Reset 21.8. Register Definitions: Peripheral Pin Select (PPS) 21.8.1. xxxPPS 21.8.2. RxyPPS 21.8.3. PPSLOCK 21.9. Register Summary: Peripheral Pin Select Module 22. CLC - Configurable Logic Cell 22.1. CLC Setup 22.1.1. Data Selection 22.1.2. Data Gating 22.1.3. Logic Function 22.1.4. Output Polarity 22.2. CLC Interrupts 22.3. Effects of a Reset 22.4. Output Mirror Copies 22.5. Operation During Sleep 22.6. CLC Setup Steps 22.7. Register Overlay 22.8. Register Definitions: Configurable Logic Cell 22.8.1. CLCSELECT 22.8.2. CLCnCON 22.8.3. CLCnPOL 22.8.4. CLCnSEL0 22.8.5. CLCnSEL1 22.8.6. CLCnSEL2 22.8.7. CLCnSEL3 22.8.8. CLCnGLS0 22.8.9. CLCnGLS1 22.8.10. CLCnGLS2 22.8.11. CLCnGLS3 22.8.12. CLCDATA 22.9. Register Summary - CLC Control 23. CLKREF - Reference Clock Output Module 23.1. Clock Source 23.1.1. Clock Synchronization 23.2. Programmable Clock Divider 23.3. Selectable Duty Cycle 23.4. Operation in Sleep Mode 23.5. Register Definitions: Reference Clock 23.5.1. CLKRCON 23.5.2. CLKRCLK 23.6. Register Summary: Reference CLK 24. TMR0 - Timer0 Module 24.1. Timer0 Operation 24.1.1. 8-bit Mode 24.1.2. 16-bit Mode 24.2. Clock Selection 24.2.1. Synchronous Mode 24.2.2. Asynchronous Mode 24.2.3. Programmable Prescaler 24.2.4. Programmable Postscaler 24.3. Timer0 Output and Interrupt 24.3.1. Timer0 Output 24.3.2. Timer0 Interrupt 24.3.3. Timer0 Example 24.4. Operation During Sleep 24.5. Register Definitions: Timer0 Control 24.5.1. T0CON0 24.5.2. T0CON1 24.5.3. TMR0H 24.5.4. TMR0L 24.6. Register Summary: Timer0 25. TMR1 - Timer1 Module with Gate Control 25.1. Timer1 Operation 25.2. Clock Source Selection 25.2.1. Internal Clock Source 25.2.2. External Clock Source 25.3. Timer1 Prescaler 25.4. Secondary Oscillator 25.5. Timer1 Operation in Asynchronous Counter Mode 25.5.1. Reading and Writing TMRx in Asynchronous Counter Mode 25.6. Timer1 16-Bit Read/Write Mode 25.7. Timer1 Gate 25.7.1. Timer1 Gate Enable 25.7.2. Timer1 Gate Source Selection 25.7.3. Timer1 Gate Toggle Mode 25.7.4. Timer1 Gate Single Pulse Mode 25.7.5. Timer1 Gate Value Status 25.7.6. Timer1 Gate Event Interrupt 25.8. Timer1 Interrupt 25.9. Timer1 Operation During Sleep 25.10. CCP Capture/Compare Time Base 25.11. CCP Special Event Trigger 25.12. Peripheral Module Disable 25.13. Register Definitions: Timer1 Control 25.13.1. TxCON 25.13.2. TxGCON 25.13.3. TxCLK 25.13.4. TxGATE 25.13.5. TMRx 25.14. Register Summary Timer 1 26. TMR2 - Timer2 Module 26.1. Timer2 Operation 26.1.1. Free-Running Period Mode 26.1.2. One-Shot Mode 26.1.3. Monostable Mode 26.2. Timer2 Output 26.3. External Reset Sources 26.4. Timer2 Interrupt 26.5. PSYNC bit 26.6. CSYNC bit 26.7. Operating Modes 26.8. Operation Examples 26.8.1. Software Gate Mode 26.8.2. Hardware Gate Mode 26.8.3. Edge-Triggered Hardware Limit Mode 26.8.4. Level-Triggered Hardware Limit Mode 26.8.5. Software Start One-Shot Mode 26.8.6. Edge-Triggered One-Shot Mode 26.8.7. Edge-Triggered Hardware Limit One-Shot Mode 26.8.8. Level Reset, Edge-Triggered Hardware Limit One-Shot Modes 26.8.9. Edge-Triggered Monostable Modes 26.8.10. Level-Triggered Hardware Limit One-Shot Modes 26.9. Timer2 Operation During Sleep 26.10. Register Definitions: Timer2 Control 26.10.1. TxTMR 26.10.2. TxPR 26.10.3. TxCON 26.10.4. TxHLT 26.10.5. TxCLKCON 26.10.6. TxRST 26.11. Register Summary - Timer2 27. SMT - Signal Measurement Timer 27.1. SMT Operation 27.1.1. Clock Source Selection 27.1.2. Signal and Window Source Selection 27.1.3. Time Base 27.1.4. Pulse Width and Period Captures 27.1.5. Status Information 27.1.6. Modes of Operation 27.1.6.1. Timer Mode 27.1.6.2. Gated Timer Mode 27.1.6.3. Period and Duty Cycle Measurement Mode 27.1.6.4. High and Low Measurement Mode 27.1.6.5. Windowed Measurement Mode 27.1.6.6. Gated Window Measurement Mode 27.1.6.7. Time-of-Flight Measurement Mode 27.1.6.8. Capture Mode 27.1.6.9. Counter Mode 27.1.6.10. Gated Counter Mode 27.1.6.11. Windowed Counter Mode 27.1.7. Interrupts 27.1.8. Operation During Sleep 27.2. Register Definitions: SMT Control 27.2.1. SMTxCON0 27.2.2. SMTxCON1 27.2.3. SMTxSTAT 27.2.4. SMTxCLK 27.2.5. SMTxWIN 27.2.6. SMTxSIG 27.2.7. SMTxTMR 27.2.8. SMTxCPR 27.2.9. SMTxCPW 27.2.10. SMTxPR 27.3. Register Summary - SMT Control 28. CCP - Capture/Compare/PWM Module 28.1. CCP Module Configuration 28.1.1. CCP Modules and Timer Resources 28.1.2. Open-Drain Output Option 28.2. Capture Mode 28.2.1. Capture Sources 28.2.2. Timer1 Mode for Capture 28.2.3. Software Interrupt Mode 28.2.4. CCP Prescaler 28.2.5. Capture During Sleep 28.3. Compare Mode 28.3.1. CCPx Pin Configuration 28.3.2. Timer1 Mode for Compare 28.3.3. Compare During Sleep 28.4. PWM Overview 28.4.1. Standard PWM Operation 28.4.2. Setup for PWM Operation 28.4.3. Timer2 Timer Resource 28.4.4. PWM Period 28.4.5. PWM Duty Cycle 28.4.6. PWM Resolution 28.4.7. Operation in Sleep Mode 28.4.8. Changes in System Clock Frequency 28.4.9. Effects of Reset 28.5. Register Definitions: CCP Control 28.5.1. CCPxCON 28.5.2. CCPxCAP 28.5.3. CCPRx 28.6. Register Summary - CCP Control 29. Capture, Compare, and PWM Timers Selection 29.1. Register Definitions: Capture, Compare, and PWM Timer Selection 29.1.1. CCPTMRS0 29.2. Register Summary - Capture, Compare, and PWM Timers Selection 30. PWM - Pulse-Width Modulator with Compare 30.1. Output Slices 30.1.1. Output Polarity 30.1.2. Operating Modes 30.1.2.1. Left Aligned Mode 30.1.2.2. Right Aligned Mode 30.1.2.3. Center Aligned Mode 30.1.2.4. Variable Alignment Mode 30.1.2.5. Compare Modes 30.1.2.5.1. Pulsed Compare Mode 30.1.2.5.2. Toggled Compare 30.1.3. Push-Pull Mode 30.2. Period Timer 30.3. Clock Sources 30.3.1. Clock Prescaler 30.4. External Period Resets 30.5. Buffered Period and Parameter Registers 30.6. Synchronizing Multiple PWMs 30.7. Interrupts 30.7.1. Period Interrupt 30.7.1.1. Period Interrupt Postscaler 30.7.2. Parameter Interrupts 30.8. Operation During Sleep 30.9. Register Definitions: PWM Control 30.9.1. PWMxERS 30.9.2. PWMxCLK 30.9.3. PWMxLDS 30.9.4. PWMxPR 30.9.5. PWMxCPRE 30.9.6. PWMxPIPOS 30.9.7. PWMxGIR 30.9.8. PWMxGIE 30.9.9. PWMxCON 30.9.10. PWMxSaCFG 30.9.11. PWMxSaP1 30.9.12. PWMxSaP2 30.9.13. PWMLOAD 30.9.14. PWMEN 30.10. Register Summary - PWM 31. CWG - Complementary Waveform Generator Module 31.1. Fundamental Operation 31.2. Operating Modes 31.2.1. Half-Bridge Mode 31.2.2. Push-Pull Mode 31.2.3. Full-Bridge Mode 31.2.3.1. Direction Change in Full-Bridge Mode 31.2.3.2. Dead-Band Delay in Full-Bridge Mode 31.2.4. Steering Modes 31.2.4.1. Synchronous Steering Mode 31.2.4.2. Asynchronous Steering Mode 31.2.4.3. Start-up Considerations 31.3. Clock Source 31.4. Selectable Input Sources 31.5. Output Control 31.5.1. CWG Output 31.5.2. Polarity Control 31.6. Dead-Band Control 31.6.1. Dead-Band Functionality In Half-Bridge Mode 31.6.2. Dead-Band Functionality In Full-Bridge Mode 31.7. Rising Edge and Reverse Dead-Band 31.8. Falling Edge and Forward Dead Band 31.9. Dead-Band Jitter 31.10. Auto-Shutdown 31.10.1. Shutdown 31.10.2. Software Generated Shutdown 31.10.3. External Input Source 31.10.4. Pin Override Levels 31.10.5. Auto-Shutdown Interrupts 31.11. Auto-Shutdown Restart 31.11.1. Software-Controlled Restart 31.11.2. Auto-Restart 31.12. Operation During Sleep 31.13. Configuring the CWG 31.14. Register Definitions: CWG Control 31.14.1. CWGxCON0 31.14.2. CWGxCON1 31.14.3. CWGxCLK 31.14.4. CWGxISM 31.14.5. CWGxSTR 31.14.6. CWGxAS0 31.14.7. CWGxAS1 31.14.8. CWGxDBR 31.14.9. CWGxDBF 31.15. Register Summary - CWG 32. NCO - Numerically Controlled Oscillator Module 32.1. NCO Operation 32.1.1. NCO Clock Sources 32.1.2. Accumulator 32.1.3. Adder 32.1.4. Increment Registers 32.2. Fixed Duty Cycle Mode 32.3. Pulse Frequency Mode 32.4. Output Polarity Control 32.5. Interrupts 32.6. Effects of a Reset 32.7. Operation in Sleep 32.8. Register Definitions: NCO 32.8.1. NCOxCON 32.8.2. NCOxCLK 32.8.3. NCOxACC 32.8.4. NCOxINC 32.9. Register Summary - NCO 33. DSM - Data Signal Modulator Module 33.1. DSM Operation 33.1.1. Modulator Signal Sources 33.1.2. Carrier Signal Sources 33.2. Carrier Synchronization 33.3. Carrier Source Polarity Select 33.4. Programmable Modulator Data 33.5. Modulated Output Polarity 33.6. Operation in Sleep Mode 33.7. Effects of a Reset 33.8. Peripheral Module Disable 33.9. Register Definitions: Modulation Control 33.9.1. MDxCON0 33.9.2. MDxCON1 33.9.3. MDxCARH 33.9.4. MDxCARL 33.9.5. MDxSRC 33.10. Register Summary - DSM 34. UART - Universal Asynchronous Receiver Transmitter with Protocol Support 34.1. UART I/O Pin Configuration 34.2. UART Asynchronous Modes 34.2.1. UART Asynchronous Transmitter 34.2.1.1. Enabling the Transmitter 34.2.1.2. Transmitting Data 34.2.1.3. Transmit Data Polarity 34.2.1.4. Transmit Interrupt Flag 34.2.1.5. TSR Status 34.2.1.6. Transmitter 7-bit Mode 34.2.1.7. Transmitter Parity Modes 34.2.1.8. Asynchronous Transmission Setup 34.2.2. UART Asynchronous Receiver 34.2.2.1. Enabling the Receiver 34.2.2.2. Receiving Data 34.2.2.3. Receive Data Polarity 34.2.2.4. Receive Interrupts 34.2.2.5. Receive Framing Error 34.2.2.6. Receiver Parity Modes 34.2.2.7. Receive FIFO Overflow 34.2.2.8. Asynchronous Reception Setup 34.2.3. Asynchronous Address Mode 34.2.3.1. Address Mode Transmit 34.2.3.2. Address Mode Receive 34.3. DMX Mode (Full-featured UARTs only) 34.3.1. DMX Controller 34.3.2. DMX Receiver 34.4. LIN Modes (Full-featured UARTs only) 34.4.1. LIN Master/Slave Mode 34.4.2. LIN Slave Mode 34.4.2.1. LIN Slave Receiver 34.4.2.2. LIN Slave Transmitter 34.5. DALI Mode (Full-featured UARTs only) 34.5.1. Control Device 34.5.2. Control Gear 34.6. General Purpose Manchester (Full-featured UARTs only) 34.7. Polarity 34.8. Stop Bits 34.8.1. Delayed Receive Interrupt 34.9. Operation After FIFO Overflow 34.10. Receive and Transmit Buffers 34.10.1. FIFO Status 34.10.2. FIFO Reset 34.11. Flow Control 34.11.1. Hardware Flow Control 34.11.2. RS-485 Transceiver Control 34.11.3. XON/XOFF Flow Control 34.12. Checksum (Full-featured UARTs only) 34.12.1. Transmit Checksum Method 34.12.2. Receive Checksum Method 34.13. Collision Detection 34.14. RX/TX Activity Time-out 34.15. Clock Accuracy With Asynchronous Operation 34.16. UART Baud Rate Generator 34.16.1. Auto-Baud Detect 34.16.2. Auto-Baud Overflow 34.16.3. Auto Wake-on-Break 34.16.3.1. Auto Wake-Up Special Considerations 34.17. Transmitting a Break 34.18. Receiving a Break 34.19. UART Operation During Sleep 34.20. Register Definitions: UART 34.20.1. UxCON0 34.20.2. UxCON1 34.20.3. UxCON2 34.20.4. UxERRIR 34.20.5. UxERRIE 34.20.6. UxUIR 34.20.7. UxFIFO 34.20.8. UxBRG 34.20.9. UxRXB 34.20.10. UxTXB 34.20.11. UxP1 34.20.12. UxP2 34.20.13. UxP3 34.20.14. UxTXCHK 34.20.15. UxRXCHK 34.21. Register Summary - UART 35. SPI - Serial Peripheral Interface Module 35.1. SPI Controls 35.2. SPI Operation 35.2.1. Enabling and Disabling the SPI Module 35.2.2. BUSY Bit 35.2.3. Transmit and Receive FIFOs 35.2.4. LSb vs. MSb-First Operation 35.2.5. Input and Output Polarity Control 35.2.6. Transfer Counter 35.2.6.1. Total Bit Count Mode (BMODE = 0) 35.2.6.2. Variable Transfer Size Mode (BMODE = 1) 35.2.6.3. Transfer Counter in Slave Mode 35.3. Master Mode 35.3.1. Full-Duplex Mode 35.3.2. Transmit Only Mode 35.3.3. Receive Only Mode 35.3.4. Transfer Off Mode 35.3.5. Master Mode Slave Select Control 35.3.5.1. Hardware Slave Select Control 35.3.5.2. Software Slave Select Control 35.3.6. Master Mode SPI Clock Configuration 35.3.6.1. SPI Clock Selection 35.3.6.2. Clock and Data Change Alignment 35.3.6.3. SCK Start-up Delay 35.4. Slave Mode 35.4.1. Slave Mode Transmit Options 35.4.1.1. SDO Drive/Tri-state 35.4.1.2. SDO Output Data 35.4.2. Slave Mode Receive Options 35.4.3. Slave Mode Slave Select 35.4.4. Slave Mode Clock Configuration 35.4.5. Daisy-Chain Configuration 35.5. SPI Operation In Sleep Mode 35.6. SPI Interrupts 35.6.1. SPI Receive Interrupt 35.6.2. SPI Transmit Interrupt 35.6.3. SPI Status Interrupts 35.6.3.1. Shift Register Empty Interrupt 35.6.3.2. Transfer Counter is Zero Interrupt 35.6.3.3. Start of Slave Select and End of Slave Select Interrupts 35.6.3.4. Receiver Overflow and Transmitter Underflow Interrupts 35.7. Register Definitions: Serial Peripheral Interface 35.7.1. SPIxCON0 35.7.2. SPIxCON1 35.7.3. SPIxCON2 35.7.4. SPIxCLK 35.7.5. SPIxBAUD 35.7.6. SPIxTCNT 35.7.7. SPIxTWIDTH 35.7.8. SPIxSTATUS 35.7.9. SPIxRXB 35.7.10. SPIxTXB 35.7.11. SPIxINTE 35.7.12. SPIxINTF 35.8. Register Summary - SPI Control 36. I2C - Inter-Integrated Circuit Module 36.1. I2C Features 36.2. I2C Terminology 36.3. I2C Module Overview 36.3.1. Byte Format 36.3.2. SDA and SCL Pins 36.3.2.1. SDA Hold Time 36.3.3. Start Condition 36.3.4. Acknowledge Sequence 36.3.5. Restart Condition 36.3.6. Stop Condition 36.3.7. Bus Timeout 36.3.8. Address Buffers 36.3.9. Transmit Buffer 36.3.10. Receive Buffer 36.3.11. Clock Stretching 36.3.11.1. Clock Stretching for Buffer Operations 36.3.11.2. Clock Stretching for Other Slave Operations 36.3.12. Data Byte Count 36.3.12.1. Auto-Load I2CxCNT 36.3.13. DMA Integration 36.3.13.1. 7-Bit Master Transmission 36.3.13.2. 10-Bit Master Transmission 36.3.13.3. 7/10-Bit Master Reception 36.3.13.4. 7-Bit Slave Transmission 36.3.13.5. 10-Bit Slave Transmission 36.3.13.6. 7/10-Bit Slave Reception 36.3.14. Interrupts 36.3.14.1. High-Level Interrupts 36.3.14.2. Condition-Specific Interrupts 36.3.15. Operation in Sleep 36.4. I2C Operation 36.4.1. I2C Slave Mode Operation 36.4.1.1. Slave Addressing Modes 36.4.1.2. General Call Addressing Support 36.4.1.3. Slave Operation in 7-Bit Addressing Modes 36.4.1.3.1. Slave Transmission (7-bit Addressing Mode) 36.4.1.3.2. Slave Reception (7-Bit Addressing Mode) 36.4.1.4. Slave Operation in 10-Bit Addressing Modes 36.4.1.4.1. Slave Transmission (10-Bit Addressing Mode) 36.4.1.4.2. Slave Reception (10-Bit Addressing Mode) 36.4.2. I2C Master Mode Operation 36.4.2.1. Bus Free Time 36.4.2.2. Master Clock Timing 36.4.2.3. Start Condition Timing 36.4.2.4. Acknowledge Sequence Timing 36.4.2.5. Restart Condition Timing 36.4.2.6. Stop Condition Timing 36.4.2.7. Master Operation in 7-Bit Addressing Modes 36.4.2.7.1. Master Transmission (7-Bit Addressing Mode) 36.4.2.7.2. Master Reception (7-Bit Addressing Mode) 36.4.2.8. Master Operation in 10-Bit Addressing Modes 36.4.2.8.1. Master Transmission (10-Bit) 36.4.2.8.2. Master Reception (10-Bit Addressing Mode) 36.4.3. I2C Multi-Master Mode Operation 36.4.3.1. Multi-Master Mode Clock Synchronization 36.4.3.2. Multi-Master Mode Bus Arbitration 36.5. Register Definitions: I2C Control 36.5.1. I2CxCON0 36.5.2. I2CxCON1 36.5.3. I2CxCON2 36.5.4. I2CxSTAT0 36.5.5. I2CxSTAT1 36.5.6. I2CxPIR 36.5.7. I2CxPIE 36.5.8. I2CxERR 36.5.9. I2CxCLK 36.5.10. I2CxCNT 36.5.11. I2CxBTO 36.5.12. I2CxADB0 36.5.13. I2CxADB1 36.5.14. I2CxADR0 36.5.15. I2CxADR1 36.5.16. I2CxADR2 36.5.17. I2CxADR3 36.5.18. I2CxTXB 36.5.19. I2CxRXB 36.6. Register Summary - I2C 37. HLVD - High/Low-Voltage Detect 37.1. Operation 37.2. Setup 37.3. Current Consumption 37.4. HLVD Start-up Time 37.5. Applications 37.6. Operation During Sleep 37.7. Operation During Idle and Doze Modes 37.8. Effects of a Reset 37.9. Register Definitions: HLVD Control 37.9.1. HLVDCON0 37.9.2. HLVDCON1 37.10. Register Summary - HLVD 38. FVR - Fixed Voltage Reference 38.1. Independent Gain Amplifiers 38.2. FVR Stabilization Period 38.3. Register Definitions: FVR 38.3.1. FVRCON 38.4. Register Summary - FVR 39. Temperature Indicator Module 39.1. Module Operation 39.1.1. Temperature Indicator Range 39.1.2. Minimum Operating VDD 39.2. Temperature Calculation 39.2.1. Higher-Order Calibration 39.3. ADC Acquisition Time 39.4. Register Definitions: Temperature Indicator 39.4.1. FVRCON 39.5. Register Summary - Temperature Indicator 40. ADCC - Analog-to-Digital Converter with Computation Module 40.1. ADC Configuration 40.1.1. Port Configuration 40.1.2. Channel Selection 40.1.3. ADC Voltage Reference 40.1.4. Conversion Clock 40.1.5. Interrupts 40.1.6. Result Formatting 40.2. ADC Operation 40.2.1. Starting a Conversion 40.2.2. Completion of a Conversion 40.2.3. ADC Operation During Sleep 40.2.4. External Trigger During Sleep 40.2.5. Auto-Conversion Trigger 40.2.6. ADC Conversion Procedure (Basic Mode) 40.3. ADC Acquisition Requirements 40.4. ADC Charge Pump 40.5. Computation Operation 40.5.1. Digital Filter/Average 40.5.2. Basic Mode 40.5.3. Accumulate Mode 40.5.4. Average Mode 40.5.5. Burst Average Mode 40.5.6. Low-Pass Filter Mode 40.5.7. Threshold Comparison 40.5.8. Repetition and Sampling Options 40.5.8.1. Continuous Sampling Mode 40.5.8.2. Double Sample Conversion 40.6. Capacitive Voltage Divider (CVD) Features 40.6.1. CVD Operation 40.6.2. Precharge Control 40.6.3. Acquisition Control for CVD (ADPRE > 0) 40.6.4. Guard Ring Outputs 40.6.5. Additional Sample-and-Hold Capacitance 40.7. Register Definitions: ADC Control 40.7.1. ADCON0 40.7.2. ADCON1 40.7.3. ADCON2 40.7.4. ADCON3 40.7.5. ADSTAT 40.7.6. ADCLK 40.7.7. ADREF 40.7.8. ADPCH 40.7.9. ADPRE 40.7.10. ADACQ 40.7.11. ADCAP 40.7.12. ADRPT 40.7.13. ADCNT 40.7.14. ADFLTR 40.7.15. ADRES 40.7.16. ADPREV 40.7.17. ADACC 40.7.18. ADSTPT 40.7.19. ADERR 40.7.20. ADLTH 40.7.21. ADUTH 40.7.22. ADACT 40.7.23. ADCP 40.8. Register Summary - ADC 41. DAC - Digital-to-Analog Converter Module 41.1. Output Voltage Selection 41.2. Ratiometric Output Level 41.3. Operation During Sleep 41.4. Effects of a Reset 41.5. Register Definitions: DAC Control 41.5.1. DACxCON 41.5.2. DACxDATL 41.6. Register Summary - DAC 42. CMP - Comparator Module 42.1. Comparator Overview 42.2. Comparator Control 42.2.1. Comparator Enable 42.2.2. Comparator Output 42.2.3. Comparator Output Polarity 42.3. Comparator Output Synchronization 42.4. Comparator Hysteresis 42.5. Comparator Interrupt 42.6. Comparator Positive Input Selection 42.7. Comparator Negative Input Selection 42.8. Comparator Response Time 42.9. Analog Input Connection Considerations 42.10. Operation in Sleep Mode 42.11. ADC Auto-Trigger Source 42.12. Register Definitions: Comparator Control 42.12.1. CMxCON0 42.12.2. CMxCON1 42.12.3. CMxNCH 42.12.4. CMxPCH 42.12.5. CMOUT 42.13. Register Summary - Comparator 43. ZCD - Zero-Cross Detection Module 43.1. External Resistor Selection 43.2. ZCD Logic Output 43.3. ZCD Logic Polarity 43.4. ZCD Interrupts 43.5. Correction for ZCPINV Offset 43.5.1. Correction by AC Coupling 43.5.2. Correction By Offset Current 43.6. Handling VPEAK Variations 43.7. Operation During Sleep 43.8. Effects of a Reset 43.9. Disabling the ZCD Module 43.10. Register Summary: ZCD 43.11. Register Definitions: ZCD Control 43.11.1. ZCDCON 44. Instruction Set Summary 44.1. Standard Instruction Set 44.1.1. Standard Instruction Set 44.2. Extended Instruction Set 44.2.1. Extended Instruction Syntax 44.2.2. Extended Instruction Set 44.2.3. Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode 44.2.3.1. Extended Instruction Syntax with Standard PIC18 Commands 44.2.4. Considerations when Enabling the Extended Instruction Set 44.2.5. Special Considerations with Microchip MPLAB® IDE Tools 45. ICSP™ - In-Circuit Serial Programming™ 45.1. High-Voltage Programming Entry Mode 45.2. Low-Voltage Programming Entry Mode 45.3. Common Programming Interfaces 46. Register Summary 47. Electrical Specifications 47.1. Absolute Maximum Ratings(†) 47.2. Standard Operating Conditions 47.3. DC Characteristics 47.3.1. Supply Voltage 47.3.2. Supply Current (IDD)(1,2,4) 47.3.3. Power-Down Current (IPD)(1,2) 47.3.4. I/O Ports 47.3.5. Memory Programming Specifications 47.3.6. Thermal Characteristics 47.4. AC Characteristics 47.4.1. External Clock/Oscillator Timing Requirements 47.4.2. Internal Oscillator Parameters(1) 47.4.3. PLL Specifications 47.4.4. I/O and CLKOUT Timing Specifications 47.4.5. Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications 47.4.6. High/Low-Voltage Detect Characteristics 47.4.7. Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) 47.4.8. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 47.4.9. Comparator Specifications 47.4.10. 8-Bit DAC Specifications 47.4.11. Fixed Voltage Reference (FVR) Specifications 47.4.12. Zero-Cross Detect (ZCD) Specifications 47.4.13. Timer0 and Timer1 External Clock Requirements 47.4.14. Capture/Compare/PWM Requirements (CCP) 47.4.15. SPI Mode Requirements 47.4.16. I2C Bus Start/Stop Bits Requirements 47.4.17. I2C Bus Data Requirements 47.4.18. Configurable Logic Cell (CLC) Characteristics 47.4.19. Temperature Indicator Requirements 48. DC and AC Characteristics Graphs and Tables 49. Packaging Information 49.1. Package Details 50. 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