5.4.4 Single-Ended, Dual Sample-and-Hold with Software Trigger with Averaging ON

In this configuration, the AFEC is defined as Single-ended, without averaging and in dual Sample-and-Hold.

In this mode, two channels are sampled at the same time.

Channel 2 is connected to the 1.0V external DC voltage source. The result of this conversion is 993mV, and matches the resulting digital code 20022 out of 65536 (16-bit resolution).

Channel 8 is connected to the 2.4V external DC voltage source. The result of this conversion is 2393mV, and matches the resulting digital code 48223 out of 65536 (16-bit resolution).

The source code for initialization is found below. Steps 1 to 5 have been described in the section AFEC Module Introduction. Steps 6 to 8 describe the additional actions to perform if the application requires offset compensation, averaging or dual Sample-and-Hold.

Single Sample-and-Hold mode is enabled by default. To enable dual Sample-and-Hold mode, the channel combination must be identified by using the table below.

Table 1. Input Pins and Channel Number in Dual Sample-and-Hold Mode
Single-Ended Input Pins	Differential Input Pins	Channel Numbers
AFE_AD0 and AFE_AD6	AFE_AD0-AD1 and AFE_AD6–AFE_AD7	CH0
AFE_AD1 and AFE_AD7	–	CH1
...	...	...
AFE_AD4 and AFE_AD10	AFE_AD4–AFE_AD5 and AFE_AD10–AFE_AD11	CH4
AFE_AD5 and AFE_AD11	–	CH5

For this application, channel 2 (composed of the channel 2 and channel 8) is the channel to be configured. Once the channel combination is identified, the Sample-and-Hold Mode register (AFEC_SHMR) must be set.

The DC offset correction must be applied on both channel 2 and channel 8 to get correct results.

static void _afe_initialization_SingleEnded_DualSH_OSR256(void) {
	
	/* Step 1: Configure the pins for AFEC. (If not already done by default) */
	/* Step 2: AFEC init */
	AFEC_Initialize( AFEC0, ID_AFEC0 );
	
	/* Step 3: AFEC Mode Register Configuration */
	AFEC_SetModeReg(AFEC0,AFEC_MR_FREERUN_OFF|AFEC_MR_TRANSFER(1)|AFEC_MR_TRACKTIM(2)| AFEC_MR_ONE| AFEC_MR_STARTUP_SUT512);
	
	/* Step 4: Enable the FAEC Dual Sample And Hold feature for the channel 2 */
	AFEC0->AFEC_SHMR |= AFEC_SHMR_DUAL2;
	
	/* Step 5	Set AFEC clock AFEC_SetClock() */
	AFEC_SetClock( AFEC0, AFE_CLK, BOARD_MCK ) ;
	
	/* Step 6	Select the active channel using the Macro definition AFEC_EnableChannel(). */
	AFEC_EnableChannel(AFEC0, TEST_CHANNEL_SINGLE_ENDED_DUALSH);	// the channel is different than in previous example.
	
	/* Step 7	Adjust the offset level of each channels */
	AFEC_SetAnalogOffset(AFEC0, TEST_CHANNEL_SINGLE_ENDED_DUALSH, CHANNEL_OFFSET);
	AFEC_SetAnalogOffset(AFEC0, 8, CHANNEL_OFFSET);
	
	/* Step 8 Enable the PGA 0 and 1 of the AFEC0 and adjust the performances by tuning the AFE Bias Current Control */
	AFEC_SetAnalogControl(AFEC0, AFEC_ACR_IBCTL(1) | AFEC_ACR_PGA0_ON | AFEC_ACR_PGA1_ON );
	
	/* Step 9 Configure the Extended Mode Register by enabling the Averaging, enabling the channel tag and using the Single Trigger Mode */
	AFEC_SetExtModeReg(AFEC0,0|AFEC_EMR_RES_OSR256|AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN| AFEC_EMR_TAG | AFEC_EMR_STM );
}