Interrupt Vectors in ATmega324PB

Table 1. Reset and Interrupt Vectors in ATmega324PB
Vector No Program Address(2) Source Interrupts definition
1 0x0000(1) RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset
2 0x0002 INT0 External Interrupt Request 0
3 0x0004 INT1 External Interrupt Request 1
4 0x0006 INT2 External Interrupt Request 2
5 0x0008 PCINT0 Pin Change Interrupt Request 0
6 0x000A PCINT1 Pin Change Interrupt Request 1
7 0x000C PCINT2 Pin Change Interrupt Request 2
8 0x000E PCINT3 Pin Change Interrupt Request 3
9 0x0010 WDT Watchdog Time-out Interrupt
10 0x0012 TIMER2_COMPA Timer/Counter2 Compare Match A
11 0x0014 TIMER2_COMPB Timer/Coutner2 Compare Match B
12 0x0016 TIMER2_OVF Timer/Counter2 Overflow
13 0x0018 TIMER1_CAPT Timer/Counter1 Capture Event
14 0x001A TIMER1_COMPA Timer/Counter1 Compare Match A
15 0x001C TIMER1_COMPB Timer/Coutner1 Compare Match B
16 0x001E TIMER1_OVF Timer/Counter1 Overflow
17 0x0020 TIMER0_COMPA Timer/Counter0 Compare Match A
18 0x0022 TIMER0_COMPB Timer/Coutner0 Compare Match B
19 0x0024 TIMER0_OVF Timer/Counter0 Overflow
20 0x0026 SPI0_STC SPI0 Serial Transfer Complete
21 0x0028 USART0_RX USART0 Rx Complete
22 0x002A USART0_UDRE USART0, Data Register Empty
23 0x002C USART0_TX USART0, Tx Complete
24 0x002E ANALOG_COMP Analog Comparator
25 0x0030 ADC ADC Conversion Complete
26 0x0032 EE_READY EEPROM Ready
27 0x0034 TWI0 TWI0 Transfer complete
28 0x0036 SPM_READY Store Program Memory Ready
29 0x0038 USART1_RX USART1 Rx Complete
30 0x003A USART1_UDRE USART1, Data Register Empty
31 0x003C USART1_TX USART0, Tx Complete
32 0x003E TIMER3_CAPT Timer/Counter3 Capture Event
33 0x0040 TIMER3_COMPA Timer/Counter3 Compare Match A
34 0x0042 TIMER3_COMPB Timer/Coutner3 Compare Match B
35 0x0044 TIMER3_OVF Timer/Counter3 Overflow
36 0x0046 USART0_START USART0 Start Frame detection
37 0x0048 USART1_START USART1 Start Frame detection
38 0x004A PCINT4 Pin Change Interrupt 4
39 0x004C CFD Crystal Failure Detection
40 0x004E PTC_EOC PTC End of Conversion
41 0x0050 PTC_WCOMP PTC Window comparator mode
42 0x0052 SPI1_STC SPI1 Serial Transfer Complete
43 0x0054 TWI1 TWI1 Transfer complete
44 0x0056 TIMER4_CAPT Timer/Counter4 Capture Event
45 0x0058 TIMER4_COMPA Timer/Counter4 Compare Match A
46 0x005A TIMER4_COMPB Timer/Coutner4 Compare Match B
47 0x005C TIMER4_OVF Timer/Counter4 Overflow
48 0x005E USART2_RX USART2 Rx Complete
49 0x0060 USART2_UDRE USART2, Data Register Empty
50 0x0062 USART2_TX USART2, Tx Complete
51 0x0064 USART2_START USART2 Start Frame detection
Note:
  1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see Memory programming
  2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

The table below shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.

Table 2. Reset and Interrupt Vectors placement
BOOTRST IVSEL Reset Address Interrupt Vectors Start Address
1 0 0x0000 0x0002
1 1 0x0000 Boot Reset Address + 0x0002
0 0 Boot Reset Address 0x0002
0 1 Boot Reset Address Boot Reset Address + 0x0002
Note: The Boot Reset Address is shown in Table Boot size configuration in Boot Loader Parameters. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address    Labels     Code                    Comments
0x00000    RESET:     ldi r16,high(RAMEND)    ; Main program start
0x00001               out SPH,r16             ; Set Stack Pointer to top of RAM
0x00002               ldi r16,low(RAMEND)
0x00003               out SPL,r16
0x00004               sei                     ; Enable interrupts
0x00005               <instr>            xxx
;
.org 0x1F002
0x1F002               jmp EXT_INT0            ; IRQ0 Handler
0x1F004               jmp EXT_INT1            ; IRQ1 Handler
...        ...         ...                    ;
0x1FO36               jmp SPM_RDY             ; SPM Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address    Labels     Code                     Comments
.org 0x0002
0x00002               jmp EXT_INT0            ; IRQ0 Handler
0x00004               jmp EXT_INT1            ; IRQ1 Handler
...          ...      ...                     ;
0x00036               jmp SPM_RDY             ; SPM Ready Handler
;
.org       0x1F000
0x1F000    RESET:     ldi r16,high(RAMEND)    ; Main program start
0x1F001               out SPH,r16             ; Set Stack Pointer to top of RAM
0x1F002               ldi r16,low(RAMEND)
0x1F003               out SPL,r16
0x1F004               sei                     ; Enable interrupts
0x1F005               <instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address    Labels      Code                     Comments
;
.org 0x1F000
0x1F000                jmp RESET               ; Reset handler
0x1F002                jmp EXT_INT0            ; IRQ0 Handler
0x1F004                jmp EXT_INT1            ; IRQ1 Handler
...        ...         ...                     ;
0x1F036                jmp SPM_RDY             ; SPM Ready Handler
;
0x1F03E    RESET:      ldi r16,high(RAMEND)    ; Main program start
0x1F03F                out SPH,r16             ; Set Stack Pointer to top of RAM
0x1F040                ldi r16,low(RAMEND)
0x1F041                out SPL,r16
0x1F042                sei                     ; Enable interrupts
0x1FO43                <instr> xxx
Parent topic: INT- Interrupts