Alternate Functions of Port D

The Port D pins with alternate functions are shown in the table below:

Table 1. Port D Pins Alternate Functions
Port Pin	Alternate Function
PD7	OC2A (Timer/Counter2 Output Compare Match A Output) XCK2 (USART2 External Clock Input/Output) SCK1 (SPI1 Bus Master clock Input) PCINT31 (Pin Change Interrupt 31)
PD6	ICP1 (Timer/Counter1 Input Capture Trigger) OC2B (Timer/Counter2 Output Compare Match B Output) SS1 (SPI1 Slave Select input) PCINT30 (Pin Change Interrupt 30)
PD5	OC1A (Timer/Counter1 Output Compare Match A Output) PCINT29 (Pin Change Interrupt 29)
PD4	OC1B (Timer/Counter1 Output Compare Match B Output) XCK1 (USART1 External Clock Input/Output) PCINT28 (Pin Change Interrupt 28)
PD3	INT1 (External Interrupt1 Input) TXD1 (USART1 Transmit Pin) PCINT27 (Pin Change Interrupt 27)
PD2	INT0 (External Interrupt0 Input) RXD1 (USART1 Receive Pin) PCINT26 (Pin Change Interrupt 26)
PD1	TXD0 (USART0 Transmit Pin) PCINT25 (Pin Change Interrupt 25)
PD0	RXD0 (USART0 Receive Pin) T3 (Timer/Counter 3 External Counter Input) PCINT24 (Pin Change Interrupt 24)

The alternate pin configuration is as follows:

OC2A/XCK2/SCK1/PCINT31 – Port D, Bit 7
- OC2A: Output Compare Match output. The PD7 pin can serve as an external output for the Timer/Counter2 Compare Match A. The PD7 pin has to be configured as an output (DDRD7 set '1') to serve this function. The OC2A pin is also the output pin for the PWM mode timer function.
- XCK2: USART2 External clock. The Data Direction Register (DDRD7) controls whether the clock is output (DDRD7 set “1”) or input (DDRD7 cleared). The XCK2 pin is active only when the USART2 operates in Synchronous mode.
- SCK1: Master Clock output, Slave Clock input pin for SPI1 channel. When the SPI1 is enabled as a Slave, this pin is configured as an input regardless of the setting of DDRD7. When the SPI1 is enabled as a Master, the data direction of this pin is controlled by DDRD7.
- PCINT31: Pin Change Interrupt source 31. The PD7 pin can serve as an external interrupt source.

ICP1/OC2B/SS1/PCINT30 – Port D, Bit 6
- ICP1: Input Capture Pin 1. The PD6 pin can act as an input capture pin for Timer/Counter1.
- OC2B: Output Compare Match B output. The PD6 pin can serve as an external output for the Timer/Counter2 Output Compare B. The pin has to be configured as an output (DDRD6 set '1') to serve this function. The OC2B pin is also the output pin for the PWM mode timer function.
- SS1: Slave Port Select input. When the SPI1 is enabled as a slave, this pin is configured as an input regardless of the setting of DDRD6. As a slave, the SPI1 is activated when this pin is driven low. When the SPI1 is enabled as a master, the data direction of this pin is controlled by DDRD6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTD6 bit.
- PCINT30: Pin Change Interrupt source 30. The PD6 pin can serve as an external interrupt source.

OC1A/PCINT29 – Port D, Bit 5
- OC1A: Output Compare Match output. The PD5 pin can serve as an external output for the Timer/Counter1 Compare Match A. The PD5 pin has to be configured as an output (DDRD5 set '1') to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.
- PCINT29: Pin Change Interrupt source 29. The PD4 pin can serve as an external interrupt source.

OC1B/XCK1/PCINT28 – Port D, Bit 4
- OC1B: Output Compare Match B output. The PD4 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDRD4 set '1') to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.
- XCK1: USART1 external clock.
- PCINT28: Pin Change Interrupt source 28. The PD4 pin can serve as an external interrupt source.

INT1/TXD1/PCINT27 – Port D, Bit 3
- INT1: External Interrupt source 1. The PD3 pin can serve as an external interrupt source.
- TXD1: Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is configured as an output regardless of the value of DDRD3.
- PCINT27: Pin Change Interrupt source 27. The PD3 pin can serve as an external interrupt source.

INT0/RXD1/PCINT26 – Port D, Bit 2
- INT0: External Interrupt source 0. The PD2 pin can serve as an external interrupt source.
- RXD1: Receive Data (Data input pin for the USART1). When the USART1 Receiver is enabled this pin is configured as an input regardless of the value of DDRD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0 bit.
- PCINT26: Pin Change Interrupt source 26. The PD2 pin can serve as an external interrupt source.

TXD0/PCINT25 – Port D, Bit 1
- TXD0: Transmit Data (Data output pin for the USART0). When the USART0 Transmitter is enabled, this pin is configured as an output regardless of the value of DDRD1.
- PCINT25: Pin Change Interrupt source 25. The PD1 pin can serve as an external interrupt source.

RXD0/PCINT24 – Port D, Bit 0
- RXD0: Receive Data (Data input pin for the USART0). When the USART0 Receiver is enabled this pin is configured as an input regardless of the value of DDRD0. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0 bit.
- T3: Timer/Counter 3 External Counter Input
- PCINT24: Pin Change Interrupt source 24. The PD0 pin can serve as an external interrupt source.

The tables below relate the alternate functions of Port D to the overriding signals shown in Figure 1.

Table 2. Overriding Signals for Alternate Functions PD7...PD4
Signal Name	PD7/OC2A/XCK2/SCK1/PCINT31	PD6/ICP1/OC2B/SS1/PCINT30	PD5/OC1A/PCINT29	PD4/OC1B/XCK1/PCINT28
PUOE	SPE1 • MSTR	SPE1 • MSTR	0	0
PUO	PORTD7 • PUD	PORTD6 • PUD	0	0
DDOE	SPE1 • MSTR	SPE1 • MSTR	0	0
DDOV	0	0	0	0
PVOE	SPE1 • MSTR OC2A ENABLE	OC2B ENABLE	OC1A ENABLE	OC1B ENABLE
PVOV	OC2A SCK1 OUTPUT	OC2B	OC1A	OC1B
DIEOE	PCINT31 • PCIE3	PCINT30 • PCIE3	PCINT29 • PCIE3	PCINT28 • PCIE3
DIEOV	1	1	1	1
DI	SCK1 INPUT PCINT31 INPUT	ICP1 INPUT SPI1 SS PCINT30 INPUT	PCINT29 INPUT T1 INPUT	PCINT28 INPUT
AIO	-	-	–	–

Table 3. Overriding Signals for Alternate Functions in PD3...PD0
Signal Name	PD3/INT1/TXD1/PCINT27	PD2/INT0/RXD1/PCINT26	PD1/TXD0/PCINT25	PD0/T3/RXD0/PCINT24
PUOE	TXEN1	RXEN1	TXEN0	RXEN0
PUO	0	PORTD2 • PUD	0	PORTD0 • PUD
DDOE	TXEN1	RXEN1	TXEN0	RXEN0
DDOV	1	0	1	0
PVOE	TXEN1	0	TXEN0	0
PVOV	TXD1	0	TXD0	0
DIEOE	INT1 ENABLE PCINT27 • PCIE3	INT2 ENABLE PCINT26 • PCIE3	PCINT25 • PCIE3	PCINT24 • PCIE3
DIEOV	1	1	1	1
DI	INT1 INPUT PCINT27 INPUT	INT0 INPUT RXD1 PCINT26 INPUT	PCINT25 INPUT	RXD0 T4 INPUT PCINT24 INPUT
AIO	–	–	–	–