Parallel Programming Characteristics

Table 1. Parallel programming characteristics, VCC = 5V ±10%.
Symbol	Parameter	Min.	Typ.	Max.	Units
V_PP	Programming Enable Voltage	11.5	-	12.5	V
I_PP	Programming Enable Current		-	250	µA
t_DVXH	Data and Control Valid before XTAL1 High	67	-	-	ns
t_XLXH	XTAL1 Low to XTAL1 High	300	-	-	ns
t_XHXL	XTAL1 Pulse Width High	150	-	-	ns
t_XLDX	Data and Control Hold after XTAL1 Low	67	-	-	ns
t_XLWL	XTAL1 Low to WR Low	0	-	-	ns
t_XLPH	XTAL1 Low to PAGEL high	0	-	-	ns
t_PLXH	PAGEL low to XTAL1 high	150	-	-	ns
t_BVPH	BS1 Valid before PAGEL High	67	-	-	ns
t_PHPL	PAGEL Pulse Width High	200	-	-	ns
t_PLBX	BS1 Hold after PAGEL Low	67	-	-	ns
t_WLBX	BS2/1 Hold after WR Low	67	-	-	ns
t_PLWL	PAGEL Low to WR Low	67	-	-	ns
t_BVWL	BS2/1 Valid to WR Low	67	-	-	ns
t_WLWH	WR Pulse Width Low	150	-	-	ns
t_WLRL	WR Low to RDY/BSY Low	0	-	1	µs
t_WLRH	WR Low to RDY/BSY High⁽¹⁾	2	-	4.5	ms
t_{WLRH_CE}	WR Low to RDY/BSY High for Chip Erase⁽²⁾	7.5	-	12	ms
t_XLOL	XTAL1 Low to OE Low	0	-	-	ns
t_BVDV	BS1 Valid to DATA valid	0	-	500
t_OLDV	OE Low to DATA Valid	-	-	500
t_OHDZ	OE High to DATA Tri-stated	-	-	500

Note:

t_WLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
t_{WLRH_CE} is valid for the Chip Erase command.

Figure 1. Parallel programming timing, including some general timing requirements.

Figure 2. Parallel programming timing, loading sequence with timing requirements

Note: The timing requirements shown in Figure 1 (that is, t_DVXH, t_XHXL, and t_XLDX) also apply to loading operation.

Figure 3. Parallel programming timing, reading sequence (within the same page) with timing requirements

Note: The timing requirements shown in Figure 1 (that is, t_DVXH, t_XHXL, and t_XLDX) also apply to loading operation.