SPI Timing Characteristics

See figures below for details.

Table 1. SPI Timing Parameters
	Description	Mode	Min	Typ	Max
1	SCK period	Master		See Table 3		ns
2	SCK high/low	Master		50% duty cycle
3	Rise/Fall time	Master		3.6
4	Setup	Master		10
5	Hold	Master		10
6	Out to SCK	Master		0.5 • t_SCK
7	SCK to out	Master		10
8	SCK to out high	Master		10
9	SS low to out	Slave		15
10	SCK period	Slave	4 • tck
11	SCK high/low⁽¹⁾	Slave	2 • tck
12	Rise/Fall time	Slave			1.6
13	Setup	Slave	10
14	Hold	Slave	10
15	SCK to out	Slave		15
16	SCK to SS high	Slave	20
17	SS high to tri-state	Slave		10
18	SS low to SCK	Salve	2 • tck

Note:

1. In SPI Programming mode the minimum SCK high/low period is: - 2t_CLCL for f_CK < 12 MHz - 3t_CLCL for f_CK > 12 MHz

Figure 1. SPI interface timing requirements (Master Mode)

SPI interface timing requirements (Slave Mode)