| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CHBUSY11 | CHBUSY10 | CHBUSY9 | CHBUSY8 | ||||
| Access | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | |||
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CHBUSY7 | CHBUSY6 | CHBUSY5 | CHBUSY4 | CHBUSY3 | CHBUSY2 | CHBUSY1 | CHBUSY0 |
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| USRRDY11 | USRRDY10 | USRRDY9 | USRRDY8 | ||||
| Access | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | |||
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| USRRDY7 | USRRDY6 | USRRDY5 | USRRDY4 | USRRDY3 | USRRDY2 | USRRDY1 | USRRDY0 |
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Channel Busy n [n = 11..0]
This bit is cleared when channel n is idle.
This bit is set if an event on channel n has not been handled by all event users connected to channel n.
User Ready for Channel n [n = 11..0]
This bit is cleared when at least one of the event users connected to the channel is not ready.
This bit is set when all event users connected to channel n are ready to handle incoming events on channel n.