Errata

The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die.

Die Revision B

OSC48M

  1. When a System Reset is applied, the OSC48MDIV register is reset, but the value is not synchronized. This may result in the system clock running too fast.
    Errata reference: 14497
    Fix/Workaround:
    Do not write OSC48MDIV to lower than 0xB.
    Do not run the device faster than 4MHz when running from internal oscillators

PORT

  1. When the PORT is defined as EVSYS.USER in a synch/resynch path, the first event is transmitted to the PORT but the acknowledgement coming from the PORT is not released. So next coming events are treated as overrun by EVSYS.
    Errata reference: 14317
    Fix/Workaround:
    None.
    Do not use the synch/resynch path, only use asynchronous path.

RTC

  1. The COUNTSYNC/CLOCKSYNC bit of the RTC.CTRLA register has no effect. Read synchronization of the COUNT/CLOCK register is always enabled.
    Errata reference: 13714
    Fix/Workaround:
    None

OSC32KCTRL

  1. At start-up and in case of clock failure detection(CFD), the auto switch by the CFD does not work if the XOSC32K is requested by the GCLK.
    Errata/Workaround
    Manually change clock from XOSC32K to another 32K source.

DAC

  1. DAC in dithering mode with right adjust data leads to INL of 16 LSBs.
    Errata reference: 14642
    Fix/Workaround:
    Use dithering with left adjusted data only

Device

  1. The SYSTICK calibration value is incorrect.
    Errata reference: 14156
    Fix/Workaround:
    The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize the Systick RELOAD value register, which should be initialized instead with a value depending on the main clock frequency and on the tick period required by the application. For a detailed description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
  2. In IDLE sleep mode, the APB and AHB clocks are not stopped if the FDPLL is running as a GCLK clock source.
    Errata reference: 13401
    Fix/Workaround:
    Disable the FDPLL before entering IDLE sleep mode.
  3. The Analog Comparators and ADC1 use the same generic clock configuration. GCLK_ADC1 must be used to configure the clock for AC as GCLK_AC is not functional.
    Errata reference: 13404
    Fix/Workaround:
    None
  4. Increased power consumption in standby sleep mode.
    Errata reference: 14100
    Fix/Workaround:
    None
  5. In I2C Slave mode, writing the CTRLB register when in the AMATCH or DRDY interrupt service routines can cause the state machine to reset.
    Errata reference: 13574
    Fix/Workaround:
    Write CTRLB.ACKACT to 0 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Write CTRLB.ACKACT to 1 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close out a transaction.
    When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit position instead of using CTRLB.CMD. The DRDY interrupt is automatically cleared by reading/writing to the DATA register in smart mode. If not in smart mode, DRDY should be cleared by writing a 1 to its bit position.
    Code replacements examples:
    Current:
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Current:
    SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Current:
    /* ACK or NACK address */
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
    Change to:
    // CMD=0x3 clears all interrupts, so to keep the result similar,
    // PREC is cleared if it was set.
    if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
    SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
  6. VREGSMOD bits have no effect in PM.STDBYCFG register. The power domain controller always operates in automatic regulator mode.
    Errata reference: 14498
    Fix/Workaround:
    None
  7. The OSC48M accuracy cannot be reached for the whole VDD range.
    Errata reference: 15342
    Fix/Workaround:
    Rev A / B: none
    Rev C: limited VDD range, according to the Electrical Characteristics chapter
    Rev D: write OSCCTRL.CAL48M register, depending on the VDD range used.
  8. The default TC selection as CCL input is not TC0, but TC4. Thus the TC selection for the CCL is TC4/TC0/TC1/TC2 instead of TC0/TC1/TC2/TC3. The TC alternate selection is TC0/TC1/TC2/TC3 instead of TC1/TC2/TC3/TC4.
    Errata reference: 13449
    Fix/Workaround:
    Use the TC input mapping described above.

FDPLL

  1. When entering standby mode, the FDPLL is still running even if not requested by any module causing extra consumption.
    Errata reference: 12244
    Fix/Workaround:
    FDPLL must be disabled before entering in standby mode and re-enabled after wake-up

DMAC

  1. When using more than one DMA channel and if one of these DMA channels has a linked descriptor, a fetch error can appear on this channel.
    Errata reference: 15670
    Fix/Workaround:
    Do not use linked descriptors, make a software link instead:
    Replace the channel which used linked descriptor by two channels DMA (with linked descriptor disabled) handled by two channels event system:
    - DMA channel 0 transfer completion is able to send a conditional event for DMA channel 1 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 0 and configuration CHCTRLB.EVACT=CBLOCK for channel 1).
    - On the transfer complete reception of the DMA channel 0, immediately re-enable the channel 0.
    - Then DMA channel 1 transfer completion is able to send a conditional event for DMA channel 0 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 1 and configuration CHCTRLB.EVACT=CBLOCK for channel 0).
    - On the transfer complete reception of the DMA channel 1, immediately re-enable the channel 1.
    - The mechanism can be launched by sending a software event on the DMA channel 0.
  2. If data is written to CRCDATAIN in two consecutive instructions, the CRC computation may be incorrect.
    Errata reference: 13507
    Fix/Workaround:
    Add a NOP instruction between each write to CRCDATAIN register.

EIC

  1. The EIC ASYNCH register is not write protected.
    Errata reference: 13848
    Fix/Workaround:
    None
  2. If the NMI pin PORT config is INPUT+PULL-UP enabled and the NMI is configured to trigger on rising edge (or both edges), the NMI exception is triggered as soon as the NMI config is written.
    Errata reference: 13074
    Fix/Workaround:
    Set the NMI pin PORT config, enable EIC in edge detection mode then disable EIC. Clear INTFLAG, then write NMI configuration.
  3. When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit.
    Errata reference: 15278
    Fix/Workaround:
    Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts.

NVMCTRL

  1. The RWW EEPROM cache is not invalidated when performing write or erase operations. Reading RWWEE cached data can result in outdated data.
    Errata reference: 14633
    Fix/Workaround:
    When the RWW EEPROM Cache is on (CTRLB.CACHEDIS=0x2 or CTRLB.CACHEDIS=0x3) invalidate the cache by issuing the INVALL NVMCTRL command immediately after issuing a RWW EEPROM write or erase operation.

EVSYS

  1. The acknowledge between an event user and the EVSYS clears the CHSTATUS.CHBUSYn bit before this information is fully propagated in the EVSYS one GCLK_EVSYS_CHANNEL_n clock cycle later. As a consequence, any generator event occurring on that channel before that extra GCLK_EVSYS_CHANNEL_n clock cycle will trigger the overrun flag.
    Errata reference: 14835
    Fix/Workaround:
    For applications using event generators other than the software event, monitor the OVR flag.
    For applications using the software event generator, wait one GCLK_EVSYS_CHANNEL_n clock cycle after the CHSTATUS.CHBUSYn bit is cleared before issuing a software event.
  2. Using synchronous, spurious overrun can appear with generic clock for the channel always on.
    Errata reference: 14532
    Fix/Workaround:
    - Request the generic clock on demand by setting the CHANNEL.ONDEMAND bit to one.
    - No penalty is introduced.

SERCOM

  1. In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors.
    Errata reference: 13852
    Fix/Workaround:
    None
  2. If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated.
    Errata reference: 13369
    Fix/Workaround:
    Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1.

CAN

  1. Description:
    (1) When a message is transmitted while CCCR.DAR = ’1’ (automatic re-transmission disabled for messages not transmitted successfully), the Event Type of the corresponding Tx Event FIFO element is ET = ""01"" instead of ET = ""10"". (2) When multiple messages are transmitted sequentially using the same Tx Buffer while CCCR.DAR = ’1’, it may happen that a newly requested transmission is not started when it is requested in the time window starting at the successful completion of the previous message and ending at the end of the intermission phase before the bus is idle again. This message is then treated as if it had lost arbitration.
    Scope:
    The errata is limited to message transmission when DAR mode is configured. Normal CAN / CAN FD operation is not affected
    Effects:
    (1) The Event Type of the associated Tx Event FIFO element is not correct. (2) When a message was transmitted successfully from a specific Tx Buffer, a following transmission using the same Tx Buffer and requested in the described time window will not be started.
    Errata reference: 13525
    Fix/Workaround:
    Do not use the same Tx Buffer for consecutive DAR transmissions or wait at least for 4 CAN bit times after successful transmission before requesting the next transmission from the same Tx Buffer.
  2. Description:
    When a CAN 2.0 frame is transmitted while CAN FD operation is enabled, a recessive stuff bit following the first reserved bit will cause a shift in the DLC for specific identifiers with the result, that a frame with faulty DLC and faulty number of data bytes is transmitted.
    Scope:
    The erratum is limited to the case when a CAN 2.0 frame is transmitted while CAN FD operation is enabled (CCCR.CME ≠ ""00""). The problem does not occur when CAN FD frames are transmitted or when CAN FD operation is disabled.
    Effects:
    In case the identifier of a transmit message ends with two dominant bits (11-bit ID) or three dominant bits (29-bit ID), bit stuffing causes the DLC to be shifted by one bit to the right. This results in transmission of a message with faulty DLC and therefore faulty number of data bytes.
    Errata reference: 13511
    Fix/Workaround:
    No workaround needed in CAN 2.0 networks, CAN Conformance Test passed. No workaround needed when only CAN FD messages are transmitted. For mixed operation (CAN 2.0 and CAN FD frames) the problematic identifiers may not be used for the transmission of CAN 2.0 frames.
  3. Description:
    When CCCR.INIT is set while the M_CAN is receiving a frame, the next received frame after resetting CCCR.INIT will cause IR.MRAF to be set.
    Scope:
    The errata is limited to the case when CCCR.INIT is set / reset while the M_CAN is receiving a frame.
    Effects:
    IR.MRAF is set when the first frame after resetting CCCR.INIT is received although that frame is received correctly.
    Errata reference: 13524
    Fix/Workaround:
    If CCCR.INIT shall be set during operation proceed as follows: (1) Issue a clock stop request by setting bit CCCR.CSR. (2) Wait until the M_CAN sets CCCR.INIT and CCCR.CSA to one.
  4. Description:
    When a CAN frame is received with bit FDF and the following res bit both recessive, the protocol controller correctly detects a Protocol Exception Event. Reception of the disturbed message is not finished, the message is discarded. If this happened, two cases have to be distinguished: (1) Message reception directly after Protocol Exception Event => When the next frame is received interrupt flag IR.MRAF is set to ’1’ although the frame has been received correctly. (2) Message transmission directly after Protocol Exception Event => When a frame is transmitted directly after a Protocol Exception Event, that frame is transmitted with faulty frame format. In this case interrupt flag IR.MRAF is not set. The frame will cause an error frame. Only the first message after a Protocol Exception Event is affected, all following messages (received or transmitted) have no problem.
    Scope:
    The errata is limited to the case when the reserved bit res after the FDF bit in CAN FD frames is received recessive.
    Effects:
    Reception directly after Protocol Exception Event => Interrupt flag IR.MRAF is set although there was no problem in accessing the Message RAM. The Message is received correctly. Transmission directly after Protocol Exception Event => Transmission of a frame with faulty frame format.
    Errata reference: 13521
    Fix/Workaround:
    None.
  5. Description:
    When CCCR.CME ≠ ""00"" and a change of the CAN operation mode is requested by writing to CCCR.CMR while frame transmission/reception is ongoing, this request may be ignored and the M_CAN remains in its previous operation mode.
    Scope:
    The errata is limited to the case when a change of the CAN operation mode from/to CAN FD operation is requested while frame transmission/reception is ongoing.
    Effects:
    In case one of the affected CAN operation mode changes is requested by writing CCCR.CMR while a frame transmission/reception is ongoing, the request is acknowledged by resetting CCCR.CMR to ""00"" but the M_CAN remains in its previous operation mode.
    Errata reference: 13518
    Fix/Workaround:
    No workaround needed in CAN 2.0 networks, CAN Conformance Test passed. No workaround needed for switching between CAN operation according to ISO11898-1 and CAN FD operation with bit rate switching. In all other cases check whether the requested CAN operation mode change has been executed by reading CCCR.FDO and CCCR.FDBS. If not, repeat command until requested mode change is signalled by CCCR.FDO and CCCR.FDBS.
  6. The CAN is not compatible with an on-demand clock source.
    Errata reference: 14406
    Fix/Workaround:
    Clear the ONDEMAND bit to zero for the oscillator source that provides the GCLK to the CAN.
  7. The CAN-FD frame format implements Bosch CAN FD Specification V1.0 and is not compatible with ISO11898-1. The CCR.NISO bit has no effect.
    Errata reference: 13757
    Fix/Workaround:
    Connect only to CAN-FD networks that support Bosch CAN FD Specification V1.0
  8. Description:
    After detecting a Message RAM Access Failure during frame transmission, interrupt flag IR.MRAF is set and the M_CAN enters Restricted Operation Mode (CCCR.ASM = ’1’). When the Restricted Operation Mode is left by writing CCCR.ASM = ’0’, it may happen, that the first frame transmitted is send out with unexpected identifier and control field. If this is a valid frame, it may happen that it is accepted and acknowledged by a receiver.
    Scope:
    The errata is limited to the case when the M_CAN has entered Restricted Operation Mode due to a Message RAM Access Failure, signaled by interrupt flag IR.MRAF.
    Effects:
    With the next transmission after leaving Restricted Operation Mode by resetting CCCR.ASM, a frame with unexpected identifier and control field is transmitted which accidentally might be accepted and acknowledged by a receiver.
    Errata reference: 13523
    Fix/Workaround:
    To recover from Restricted Operation Mode proceed as follows: (1) Cancel all pending transmission requests by writing 0hFFFF FFFF to register TXBCR. (2) Issue a clock stop request by setting bit CCCR.CSR. (3) Wait until the M_CAN sets CCCR.INIT and CCCR.CSA to one. (4) First reset CCCR.CSR. (5) Then reset CCCR.INIT. (6) Wait until CCCR.INIT is read as zero. (7) Issue a second clock stop request by setting bit CCCR.CSR. (8) Wait until the M_CAN sets CCCR.INIT and CCCR.CSA to one. (9) Set CCCR.CCE, reset CCCR.CSR, and reset CCCR.ASM. (10) Restart M_CAN by writing CCCR.INIT = ’0’. (11) Configure the CAN operation mode by writing to CCCR.CMR. (12) Request the transmissions cancelled by step one.
  9. Description:
    When CCCR.CCE is set while the M_CAN Tx Handler is scanning the Message RAM for Tx Buffers with pending transmission requests (bits TXBRP.TRPnn set), register TXBRP is reset and the Tx Handler FSM is halted. After CCCR.INIT and CCCR.CCE have been reset by the Host, the M_CAN is unable to transmit messages. When the Host requests a transmission by writing to register TXBAR, the respective Tx Buffer Request Pending bit in register TXBRP is set, but the Tx Handler will not start the requested transmission.
    Scope:
    The errata is limited to the case when CCCR.CCE is set while the M_CAN Tx Handler is scanning the Message RAM.
    Effects:
    When CCCR.CCE is set while a Tx scan is in progress, the Tx Handler FSM stops. After CCCR.INIT and CCCR.CCE are reset, the Tx Handler FSM does not execute transmission requests.
    Errata reference: 13526
    Fix/Workaround:
    (1) Cancel all pending transmission requests by writing 0hFFFF FFFF to register TXBCR. (2) Issue a clock stop request by setting bit CCCR.CSR. (3) Wait until the M_CAN sets CCCR.INIT and CCCR.CSA to one. (4) First reset CCCR.CSR. (5) Then reset CCCR.INIT. (6) Wait until CCCR.INIT is read as zero. (7) Issue a second clock stop request by setting bit CCCR.CSR. (8) Wait until the M_CAN sets CCCR.INIT and CCCR.CSA to one. (9) Set CCCR.CCE and reset CCCR.CSR.
  10. Description:
    When a CAN 2.0 frame with a recessive stuff bit following the first reserved bit is received while CAN FD operation is enabled and a transmission is pending, the M_CAN will internally overwrites the received arbitration bits with the pending transmission’s arbitration bits.
    Scope:
    The erratum is limited to the case when CAN 2.0 frames with specific identifiers causing the described stuff bit are received while CAN FD operation is enabled (CCCR.CME ≠ ""00""). The problem does not occur when CAN FD operation is disabled.
    Effects:
    In case the identifier of a received data frame ends with two dominant bits (11-bit ID) or three dominant bits (29-bit ID), there will be a recessive stuff bit after the first reserved bit. This causes the falsification of the received arbitration bits if a transmission is pending. In case the pending transmission is a remote frame, the received data frame is treated as a received remote frame which will cause a format or CRC error resulting in an error frame. In case the pending transmission is a data frame, the incoming frame is received and is presented to the receive message handler with the identifier of the pending transmit message. Depending on the configuration of the acceptance filtering, the frame may be stored in an Rx Buffer or Rx FIFO.
    Errata reference: 13519
    Fix/Workaround:
    No workaround needed in CAN 2.0 networks, CAN Conformance Test passed. No workaround needed when only CAN FD frames are received. For mixed operation (CAN 2.0 and CAN FD frames) the problematic identifiers may not be used.
  11. Description:
    When BTP.TSEG2 and BTP.BRP are both zero and the M_CAN transmits a frame, the FDF bit in CAN FD format (reserved bit in Classic CAN format) in the control field may be falsified. The effect is different for frames to be transmitted in Classic CAN format and for frames to be transmitted in CAN FD format. Transmission of Classic CAN Frame => When BTP.TSEG2 and BTP.BRP are both zero and the M_CAN transmits a Classic CAN frame (CCCR.CME = ""00"") with a 29-bit identifier where the MSB (ID28) is ’1’, the reserved bit following the RTR bit will be transmitted recessive instead of dominant while the rest of the frame is transmitted in Classic CAN format. Transmission of CAN FD Frame => When BTP.TSEG2 and BTP.BRP are both zero and the M_CAN transmits a CAN FD frame with a 29-bit identifier where the MSB (ID28) is ’0’ or a CAN FD frame with 11-bit identifier, the FDF bit of the frame is transmitted dominant instead of recessive, the rest of the frame is transmitted in Classic CAN format with a falsified DLC.
    Scope:
    The erratum is limited to the case when in the bit time configuration for Classic CAN operation and the Arbitration Phase in CAN FD operation BTP.TSEG2 and BTP.BRP are both zero. This configures the time segment after the sample point to the length of one time quantum and the length of the time quantum to one clock period. This is an unusual configuration.
    Effects:
    Transmission of Classic CAN Frame => When a Classic CAN frame is received by a CAN FD enabled receiving node it will interpret the falsified reserved bit as FDF bit. If this bit is recessive instead of dominant, the frame will be interpreted as CAN FD frame. In this case the receiving node will respond with an error frame when it detects that the rest of the frame is not in CAN FD format. A strictly Classic CAN receiving node will interpret the recessive FDF bit as reserved bit, ignore its actual value and will receive this frame correctly without detecting an error. Transmission of CAN FD Frame => When the M_CAN wants to transmit a CAN FD frame, it transmits the FDF bit dominant instead of recessive and the rest of the frame in Classic CAN format with a falsified DLC.
    Errata reference: 13520
    Fix/Workaround:
    Do not use bit timing configurations where BTP.TSEG2 and BTP.BRP are both zero for CAN FD communication.
  12. Description:
    When CCCR.CMR is changed during start of transmission, the following may happen: (1) Classic CAN -> CAN FD with bit rate switching => When the Tx Event FIFO is used, bits EDL and BRS of the related Tx Event FIFO element do not match with the transmitted frame type. They signal a CAN FD frame with bit rate switching (both set to one) while a Classic CAN frame was transmitted. (2) Classic CAN -> CAN FD without bit rate switching => When the Tx Event FIFO is used, bit EDL of the related Tx Event FIFO element does not match with the transmitted frame type. It signals a CAN FD frame while a Classic CAN frame was transmitted. (3) CAN FD with bit rate switching -> CAN FD without bit rate switching => When the Tx Event FIFO is used, bit BRS of the related Tx Event FIFO element does not match with the transmitted frame type. It signals a CAN FD frame without bit rate switching while a CAN FD frame with bit rate switching was transmitted. (4) CAN FD without bit rate switching -> CAN FD with bit rate switching => When the Tx Event FIFO is used, bit BRS of the related Tx Event FIFO element does not match with the transmitted frame type. It signals a CAN FD frame with bit rate switching while a CAN FD frame without bit rate switching was transmitted. (5) CAN FD with/without bit rate switching -> Classic CAN => IR.MRAF is set, the M_CAN switches to Restricted Operation Mode, and the transmission is aborted.
    Scope:
    The errata is limited to the case when the CAN operation mode is changed during start of transmission.
    Effects:
    Tx Event FIFO element faulty (cases 1,2,3,4) or interrupt flag IR.MRAF set, Restricted Operation Mode entered, and transmission aborted (case 5).
    Errata reference: 13522
    Fix/Workaround:
    Do not change the CAN operation mode by writing to CCCR.CMR as long as there are pending transmission requests (TXBRP.TRPnn = ’1’).

TC

  1. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15056
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBuf with a new value, the STATUS.xxBUFV flag must be cleared successively two times.
  2. A capture overflow can occur without INTFLAG.ERR being set if a new capture occurs within 3 APB clock periods + 3 generic clock periods after a previous capture.
    Errata reference: 13367
    Fix/Workaround:
    The delay between two capture events must be longer than 3 APB clock periods + 3 generic clock periods.
  3. The input capture on IO pins does not work.
    Errata reference: 14024
    Fix/Workaround:
    Use the input capture through TC event and use the EIC or CCL as event generators.

TCC

  1. FCTRLX.CAPTURE[CAPTMARK] does not work as described in the datasheet. CAPTMARK cannot be used to identify captured values triggered by fault inputs source A or B on the same channel.
    Errata reference: 13316
    Fix/Workaround:
    Use two different channels to timestamp FaultA and FaultB.
  2. A capture overflow can occur without INTFLAG.ERR being set if a new capture occurs within 3 APB clocks + 3 generic Clock periods from a previous capture.
    Errata reference: 13366
    Fix/Workaround:
    The delay between two capture events must be longer than 3 APB clock periods + 3 generic clock periods.
  3. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15057
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBUF with a new value, the STATUS.xxBUFV flag must be cleared successively two times.
  4. Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) doesn’t work if an upper channel is not in one of these mode. Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN, and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
    Errata reference: 14817
    Fix/Workaround:
    Basic capture mode must be set in lower channel and advance capture mode in upper channel.
    Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN, CC[3]=CAPTMAX
    All capture will be done as expected.
  5. When the circular buffer is enabled, an APB clock is requested to update the corresponding APB register. If all masters in the system (CPU, DMA) are disabled, the APB clock is never provided to the TCC, making the circular buffer feature not functional in standby sleep mode.
    Errata reference: 12269
    Fix/Workaround:
    Keep a master enabled in the system (enable DMA, or do not enable standby sleep mode when circular buffer is enabled).
  6. In RAMP 2 mode with Fault keep, qualified and restart:
    If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can have two restarts.
    Errata reference: 13262
    Fix/Workaround:
    Avoid faults few cycles before the end or the beginning of a ramp.

CCL

  1. The reset of the RS latch is not functional. The latch can only be cleared by disabling the LUT.
    Errata reference: 14043
    Fix/Workaround:
    None

AC

  1. Hysteresis is only present for a falling (1->0) transition of the comparator output.
    Errata reference: 13712
    Fix/Workaround:
    None

ADC

  1. Once set, the ADC.SWTRIG.START will not be cleared until the Microcontroller is reset.
    Errata reference: 14094
    Fix/Workaround:
    None
  2. When window monitor is enabled and its output is 0, the ADC GCLK is kept running. Power consumption will be higher than expected in sleep modes
    Errata reference: 14449
    Fix/Workaround:
    None
  3. The LSB of ADC result is stuck at zero, in unipolar mode for 8-bit and 10-bit resolution.
    Errata reference: 14431
    Fix/Workaround:
    Use 12-bit resolution and take only least 8 bits or 10 bits, if necessary.
  4. If a synchronized event is received during an ADC conversion, the ADC will not acknowledge the event, causing a stall of the event channel.
    Errata reference: 14795
    Fix/Workaround:
    When using events with the ADC, only the asynchronous path from the Event System must be used.

SDADC

  1. The default value of zero in GAINCORR causes RESULT to be zero. The default value of zero in CTRLB.SKPCNT generates invalid data on the first two conversions
    Errata reference: 14416
    Fix/Workaround:
    Write GAINCORR to 1 before running any conversions. Write CTRLB.SKPCNT to 2 before running single conversions.
  2. If the APB clock is not 2x or higher than the Generic Clock frequency, the first input conversion in a sequence will be invalid.
    Errata reference: 14367
    Fix/Workaround:
    The APB clock must be twice the generic clock frequency or higher, or the prescaler must be configured to provide a similar ratio.

SDADC

  1. Poor INL is observed when the SDADC input signal is close to VREF.
    Errata reference: 15084
    Fix/Workaround:
    SDADC Differential Input Voltage Range should be limited to +/- 0.7.VREF (and not +/- VREF).
    SDADC Single-Ended Input Voltage Range should be limited to 0 to 0.7.VREF (and not 0 to VREF).

PTC

  1. The PTC generic clock is always requested during standby when RUNSTDBY is set to one. Power consumption will be higher if the PTC is enabled during standby sleep mode even if no conversion is on-going.
    Errata reference: 14370
    Fix/workaround
    Disable PTC in standby mode to reduce power consumption

Die Revision C

Device

  1. The OSC48M accuracy cannot be reached for the whole VDD range.
    Errata reference: 15342
    Fix/Workaround:
    Rev A / B: none
    Rev C: limited VDD range, according to the Electrical Characteristics chapter
    Rev D: write OSCCTRL.CAL48M register, depending on the VDD range used.

FDPLL96M

  1. The FDPLL96M exhibits high period jitter and is not suitable for accurate clocking. Accurate clocking is limited to 32MHz and below via XOSC.
    Errata reference: 15174
    Fix/Workaround:
    Connect a XTAL of up to 32MHz to XOSC for a high speed accurate clock source. OSC48M may be used for frequencies up to 48MHz when less accuracy is required.

DMAC

  1. When using more than one DMA channel and if one of these DMA channels has a linked descriptor, a fetch error can appear on this channel.
    Errata reference: 15670
    Fix/Workaround:
    Do not use linked descriptors, make a software link instead:
    Replace the channel which used linked descriptor by two channels DMA (with linked descriptor disabled) handled by two channels event system:
    - DMA channel 0 transfer completion is able to send a conditional event for DMA channel 1 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 0 and configuration CHCTRLB.EVACT=CBLOCK for channel 1).
    - On the transfer complete reception of the DMA channel 0, immediately re-enable the channel 0.
    - Then DMA channel 1 transfer completion is able to send a conditional event for DMA channel 0 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 1 and configuration CHCTRLB.EVACT=CBLOCK for channel 0).
    - On the transfer complete reception of the DMA channel 1, immediately re-enable the channel 1.
    - The mechanism can be launched by sending a software event on the DMA channel 0.

EIC

  1. When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit.
    Errata reference: 15278
    Fix/Workaround:
    Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts.

NVMCTRL

  1. The RWW EEPROM cache is not invalidated when performing write or erase operations. Reading RWWEE cached data can result in outdated data.
    Errata reference: 14633
    Fix/Workaround:
    When the RWW EEPROM Cache is on (CTRLB.CACHEDIS=0x2 or CTRLB.CACHEDIS=0x3) invalidate the cache by issuing the INVALL NVMCTRL command immediately after issuing a RWW EEPROM write or erase operation.

EVSYS

  1. The acknowledge between an event user and the EVSYS clears the CHSTATUS.CHBUSYn bit before this information is fully propagated in the EVSYS one GCLK_EVSYS_CHANNEL_n clock cycle later. As a consequence, any generator event occurring on that channel before that extra GCLK_EVSYS_CHANNEL_n clock cycle will trigger the overrun flag.
    Errata reference: 14835
    Fix/Workaround:
    For applications using event generators other than the software event, monitor the OVR flag.
    For applications using the software event generator, wait one GCLK_EVSYS_CHANNEL_n clock cycle after the CHSTATUS.CHBUSYn bit is cleared before issuing a software event.
  2. Using synchronous, spurious overrun can appear with generic clock for the channel always on.
    Errata reference: 14532
    Fix/Workaround:
    - Request the generic clock on demand by setting the CHANNEL.ONDEMAND bit to one.
    - No penalty is introduced.

CAN

  1. Description:
    When edge filtering is activated (CCCR.EFBI=’1’) and when the end of the integration phase coincides with a falling edge at the Rx input pin itmay happen, that the CAN synchronizes itself wrongly and does not correctly receive the first bit of the frame. In this case the CRC will detect that the first bit was received incorrectly, it will rate the received FD frame as faulty and an error frame will be send.
    The issue only occurs, when there is a falling edge at the Rx input pin (CAN_RX) within the last time quantum (tq) before the end of the integration phase. The last time quantum of the integration phase is at the sample point of the 11th recessive bit of the integration phase. When the edge filtering is enabled, the bit timing logic of the CAN sees the Rx input signal delayed by the edge filtering. When the integration phase ends, the edge filtering is automatically disabled. This affects the reset of the FD CRC registers at the beginning of the frame. The Classical CRC register is not affected, so this issue does not affect the reception of Classical frames.
    In CAN communication, The CAN may enter integrating state (either by resetting the CCCR.INIT or by protocol exception event) while a frame is active on the bus. In this case the 11 recessive bits are counted between the acknowledge bit and the following start of frame. All nodes have synchronized at the beginning of the dominant acknowledge bit. This means that the edge of the following start of frame bit cannot fall on the sample point, so the issue does not occur. The issue occurs only when the CAN is, by local errors, mis-synchronized with regard to the other nodes.
    Glitch filtering as specified in ISO 11898-1:2015 is fully functional.
    Edge filtering was introduced for applications where the data bit time is at least two tq (of nominal bit time) long. In that case, edge filtering requires at least two consecutive dominant time quanta before the counter counting the 11 recessive bits for idle detection is restarted. This means edge filtering covers the theoretical case of occasional 1-tq-long dominant spikes on the CAN bus that would delay idle detection. Repeated dominant spikes on the CAN bus would disturb all CAN communication, so the filtering to speed up idle detection would not help network performance.
    When this rare event occurs, the CAN sends an error frame and the sender of the affected frame retransmits the frame. When the retransmitted frame is received, the CAN has left integration phase and the frame will be received correctly. Edge filtering is only applied during integration phase, it is never used during normal operation. As integration phase is very short with respect to ""active communication time"", the impact on total error frame rate is negligible. The issue has no impact on data integrity.
    The CAN enters integration phase under the following conditions:
    * when CCCR.INIT is set to ’0’ after start-up
    * after a protocol exception event (only when CCCR.PXHD = ’0’)
    Scope:
    The erratum is limited to FD frame reception when edge filtering is active (CCCR.EFBI=’1’) and when the end of the integration phase coincides with a falling edge at the Rx input pin.
    Effects:
    The calculated CRC value does not match the CRC value of the received FD fram and the CAN sends an error frame. After retransmission the frame is received correctly.
    Errata reference: 14724
    Fix/Workaround:
    Disable edge filtering or wait on retransmission in case this rare event happens.

TC

  1. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15056
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBuf with a new value, the STATUS.xxBUFV flag must be cleared successively two times.

TCC

  1. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15057
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBUF with a new value, the STATUS.xxBUFV flag must be cleared successively two times.
  2. Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) doesn’t work if an upper channel is not in one of these mode. Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN, and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
    Errata reference: 14817
    Fix/Workaround:
    Basic capture mode must be set in lower channel and advance capture mode in upper channel.
    Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN, CC[3]=CAPTMAX
    All capture will be done as expected.

AC

  1. Low power mode (COMPCTRLn.SPEED = 0x0) with Hysteresis enabled (COMPCTRLn.HYSTEN = 0x1) may result in undesired behavior of the AC.
    Errata reference: 15714
    Fix/Workaround:
    Do not use AC Low Power mode (COMPCTRLn.SPEED = 0x0) and hysteresis (COMPCTRLn.HYSTEN = 0x1) together. Use only one of these features to avoid incorrect AC behavior.

ADC

  1. If a synchronized event is received during an ADC conversion, the ADC will not acknowledge the event, causing a stall of the event channel.
    Errata reference: 14795
    Fix/Workaround:
    When using events with the ADC, only the asynchronous path from the Event System must be used.

SDADC

  1. Poor INL is observed when the SDADC input signal is close to VREF.
    Errata reference: 15084
    Fix/Workaround:
    SDADC Differential Input Voltage Range should be limited to +/- 0.7.VREF (and not +/- VREF).
    SDADC Single-Ended Input Voltage Range should be limited to 0 to 0.7.VREF (and not 0 to VREF).

Die Revision D

Device

  1. The OSC48M accuracy cannot be reached for the whole VDD range.
    Errata reference: 15342
    Fix/Workaround:
    Rev A / B: none
    Rev C: limited VDD range, according to the Electrical Characteristics chapter
    Rev D: write OSCCTRL.CAL48M register, depending on the VDD range used.

DMAC

  1. When using more than one DMA channel and if one of these DMA channels has a linked descriptor, a fetch error can appear on this channel.
    Errata reference: 15670
    Fix/Workaround:
    Do not use linked descriptors, make a software link instead:
    Replace the channel which used linked descriptor by two channels DMA (with linked descriptor disabled) handled by two channels event system:
    - DMA channel 0 transfer completion is able to send a conditional event for DMA channel 1 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 0 and configuration CHCTRLB.EVACT=CBLOCK for channel 1).
    - On the transfer complete reception of the DMA channel 0, immediately re-enable the channel 0.
    - Then DMA channel 1 transfer completion is able to send a conditional event for DMA channel 0 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 1 and configuration CHCTRLB.EVACT=CBLOCK for channel 0).
    - On the transfer complete reception of the DMA channel 1, immediately re-enable the channel 1.
    - The mechanism can be launched by sending a software event on the DMA channel 0.

EIC

  1. When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit.
    Errata reference: 15278
    Fix/Workaround:
    Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts.

NVMCTRL

  1. The RWW EEPROM cache is not invalidated when performing write or erase operations. Reading RWWEE cached data can result in outdated data.
    Errata reference: 14633
    Fix/Workaround:
    When the RWW EEPROM Cache is on (CTRLB.CACHEDIS=0x2 or CTRLB.CACHEDIS=0x3) invalidate the cache by issuing the INVALL NVMCTRL command immediately after issuing a RWW EEPROM write or erase operation.

EVSYS

  1. The acknowledge between an event user and the EVSYS clears the CHSTATUS.CHBUSYn bit before this information is fully propagated in the EVSYS one GCLK_EVSYS_CHANNEL_n clock cycle later. As a consequence, any generator event occurring on that channel before that extra GCLK_EVSYS_CHANNEL_n clock cycle will trigger the overrun flag.
    Errata reference: 14835
    Fix/Workaround:
    For applications using event generators other than the software event, monitor the OVR flag.
    For applications using the software event generator, wait one GCLK_EVSYS_CHANNEL_n clock cycle after the CHSTATUS.CHBUSYn bit is cleared before issuing a software event.
  2. Using synchronous, spurious overrun can appear with generic clock for the channel always on.
    Errata reference: 14532
    Fix/Workaround:
    - Request the generic clock on demand by setting the CHANNEL.ONDEMAND bit to one.
    - No penalty is introduced.

CAN

  1. Description:
    When edge filtering is activated (CCCR.EFBI=’1’) and when the end of the integration phase coincides with a falling edge at the Rx input pin itmay happen, that the CAN synchronizes itself wrongly and does not correctly receive the first bit of the frame. In this case the CRC will detect that the first bit was received incorrectly, it will rate the received FD frame as faulty and an error frame will be send.
    The issue only occurs, when there is a falling edge at the Rx input pin (CAN_RX) within the last time quantum (tq) before the end of the integration phase. The last time quantum of the integration phase is at the sample point of the 11th recessive bit of the integration phase. When the edge filtering is enabled, the bit timing logic of the CAN sees the Rx input signal delayed by the edge filtering. When the integration phase ends, the edge filtering is automatically disabled. This affects the reset of the FD CRC registers at the beginning of the frame. The Classical CRC register is not affected, so this issue does not affect the reception of Classical frames.
    In CAN communication, The CAN may enter integrating state (either by resetting the CCCR.INIT or by protocol exception event) while a frame is active on the bus. In this case the 11 recessive bits are counted between the acknowledge bit and the following start of frame. All nodes have synchronized at the beginning of the dominant acknowledge bit. This means that the edge of the following start of frame bit cannot fall on the sample point, so the issue does not occur. The issue occurs only when the CAN is, by local errors, mis-synchronized with regard to the other nodes.
    Glitch filtering as specified in ISO 11898-1:2015 is fully functional.
    Edge filtering was introduced for applications where the data bit time is at least two tq (of nominal bit time) long. In that case, edge filtering requires at least two consecutive dominant time quanta before the counter counting the 11 recessive bits for idle detection is restarted. This means edge filtering covers the theoretical case of occasional 1-tq-long dominant spikes on the CAN bus that would delay idle detection. Repeated dominant spikes on the CAN bus would disturb all CAN communication, so the filtering to speed up idle detection would not help network performance.
    When this rare event occurs, the CAN sends an error frame and the sender of the affected frame retransmits the frame. When the retransmitted frame is received, the CAN has left integration phase and the frame will be received correctly. Edge filtering is only applied during integration phase, it is never used during normal operation. As integration phase is very short with respect to ""active communication time"", the impact on total error frame rate is negligible. The issue has no impact on data integrity.
    The CAN enters integration phase under the following conditions:
    * when CCCR.INIT is set to ’0’ after start-up
    * after a protocol exception event (only when CCCR.PXHD = ’0’)
    Scope:
    The erratum is limited to FD frame reception when edge filtering is active (CCCR.EFBI=’1’) and when the end of the integration phase coincides with a falling edge at the Rx input pin.
    Effects:
    The calculated CRC value does not match the CRC value of the received FD fram and the CAN sends an error frame. After retransmission the frame is received correctly.
    Errata reference: 14724
    Fix/Workaround:
    Disable edge filtering or wait on retransmission in case this rare event happens.

TC

  1. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15056
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBuf with a new value, the STATUS.xxBUFV flag must be cleared successively two times.

TCC

  1. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15057
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBUF with a new value, the STATUS.xxBUFV flag must be cleared successively two times.
  2. Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) doesn’t work if an upper channel is not in one of these mode. Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN, and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
    Errata reference: 14817
    Fix/Workaround:
    Basic capture mode must be set in lower channel and advance capture mode in upper channel.
    Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN, CC[3]=CAPTMAX
    All capture will be done as expected.

AC

  1. Low power mode (COMPCTRLn.SPEED = 0x0) with Hysteresis enabled (COMPCTRLn.HYSTEN = 0x1) may result in undesired behavior of the AC.
    Errata reference: 15714
    Fix/Workaround:
    Do not use AC Low Power mode (COMPCTRLn.SPEED = 0x0) and hysteresis (COMPCTRLn.HYSTEN = 0x1) together. Use only one of these features to avoid incorrect AC behavior.

ADC

  1. If a synchronized event is received during an ADC conversion, the ADC will not acknowledge the event, causing a stall of the event channel.
    Errata reference: 14795
    Fix/Workaround:
    When using events with the ADC, only the asynchronous path from the Event System must be used.

SDADC

  1. Poor INL is observed when the SDADC input signal is close to VREF.
    Errata reference: 15084
    Fix/Workaround:
    SDADC Differential Input Voltage Range should be limited to +/- 0.7.VREF (and not +/- VREF).
    SDADC Single-Ended Input Voltage Range should be limited to 0 to 0.7.VREF (and not 0 to VREF).