Interrupt
The flags are set when one of the listed conditions is detected (edge-sensitive). A flag is cleared by writing a 1 to the corresponding bit field. Writing a 0 has no effect. A hard reset will clear the register.
Name:
IR
Offset:
0x50
Reset:
0x00000000
Access:
-
Bit3130292827262524
ARAPEDPEAWDIBOEW
AccessR/WR/WR/WR/WR/WR/W
Reset000000
Bit2322212019181716
EPELOBEUBECDRXTOOMRAFTSW
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit15141312111098
TEFLTEFFTEFWTEFNTFETCFTCHPM
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit76543210
RF1LRF1FRF1WRF1NRF0LRF0FRF0WRF0N
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000

Bit 29 – ARA: Access to Reserved Address

Access to Reserved Address

ValueDescription
0 No access to reserved address occurred.
1 Access to reserved address occurred.

Bit 28 – PED: Protocol Error in Data Phase

Protocol Error in Data Phase

ValueDescription
0 No protocol error in data phase.
1 Protocol error in data phase detected (PSR.DLEC != 0,7).

Bit 27 – PEA: Protocol Error in Arbitration Phase

Protocol Error in Arbitration Phase

ValueDescription
0 No protocol error in arbitration phase.
1 Protocol error in arbitration phase detected (PSR.LEC != 0,7).

Bit 26 – WDI: Watchdog Interrupt

Watchdog Interrupt

ValueDescription
0 No Message RAM Watchdog event occurred.
1 Message RAM Watchdog event due to missing READY.

Bit 25 – BO: Bus_Off Status

Bus_Off Status

ValueDescription
0 Bus_Off status unchanged.
1 Bus_Off status changed.

Bit 24 – EW: Error Warning Status

Error Warning Status

ValueDescription
0 Error_Warning status unchanged.
1 Error_Warning status changed.

Bit 23 – EP: Error Passive

Error Passive

ValueDescription
0 Error_Passive status unchanged.
1 Error_Passive status changed.

Bit 22 – ELO: Error Logging Overflow

Error Logging Overflow

ValueDescription
0 CAN Error Logging Counter did not overflow.
1 Overflow of CAN Error Logging Counter occurred.

Bit 21 – BEU: Bit Error Uncorrected

Bit Error Uncorrected

Message RAM bit error detected, uncorrected. Generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit sets CCCR.INIT to 1. This is done to avoid transmission of corrupted data.
ValueDescription
0 Not bit error detected when reading from Message RAM.
1 Bit error detected, uncorrected (e.g. parity logic).

Bit 20 – BEC: Bit Error Corrected

Bit Error Corrected

Message RAM bit error detected and corrected. Generated by an optional external parity / ECC logic attached to the Message RAM.
ValueDescription
0 Not bit error detected when reading from Message RAM.
1 Bit error detected and corrected (e.g. ECC).

Bit 19 – DRX: Message stored to Dedicated Rx Buffer

Message stored to Dedicated Rx Buffer

The flag is set whenever a received message has been stored into a dedicated Rx Buffer.
ValueDescription
0 No Rx Buffer updated.
1 At least one received message stored into a Rx Buffer.

Bit 18 – TOO: Timeout Occurred

Timeout Occurred

ValueDescription
0 No timeout.
1 Timeout reached.

Bit 17 – MRAF: Message RAM Access Failure

Message RAM Access Failure

The flag is set, when the Rx Handler

  • has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
  • was not able to write a message to the Message RAM. In this case message storage is aborted.

In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.

The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the CAN is switched into Restricted Operation Mode. To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM.

ValueDescription
0 No Message RAM access failure occurred.
1 Message RAM access failure occurred.

Bit 16 – TSW: Timestamp Wraparound

Timestamp Wraparound

ValueDescription
0 No timestamp counter wrap-around.
1 Timestamp counter wrapped around.

Bit 15 – TEFL: Tx Event FIFO Element Lost

Tx Event FIFO Element Lost

ValueDescription
0 No Tx Event FIFO element lost.
1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.

Bit 14 – TEFF: Tx Event FIFO Full

Tx Event FIFO Full

ValueDescription
0 Tx Event FIFO not full.
1 Tx Event FIFO full.

Bit 13 – TEFW: Tx Event FIFO Watermark Reached

Tx Event FIFO Watermark Reached

ValueDescription
0 Tx Event FIFO fill level below watermark.
1 Tx Event FIFO fill level reached watermark.

Bit 12 – TEFN: Tx Event FIFO New Entry

Tx Event FIFO New Entry

ValueDescription
0 Tx Event FIFO unchanged.
1 Tx Handler wrote Tx Event FIFO element.

Bit 11 – TFE: Tx FIFO Empty

Tx FIFO Empty

ValueDescription
0 Tx FIFO non-empty.
1 Tx FIFO empty.

Bit 10 – TCF: Transmission Cancellation Finished

Transmission Cancellation Finished

ValueDescription
0 No transmission cancellation finished.
1 Transmission cancellation finished.

Bit 9 – TC: Timestamp Completed

Timestamp Completed

ValueDescription
0 No transmission completed.
1 Transmission completed.

Bit 8 – HPM: High Priority Message

High Priority Message

ValueDescription
0 No high priority message received.
1 High priority message received.

Bit 7 – RF1L: Rx FIFO 1 Message Lost

Rx FIFO 1 Message Lost

ValueDescription
0 No Rx FIFO 1 message lost.
1 Rx FIFO 1 message lost. also set after write attempt to Rx FIFO 1 of size zero.

Bit 6 – RF1F: Rx FIFO 1 Full

Rx FIFO 1 Full

ValueDescription
0 Rx FIFO 1 not full.
1 Rx FIFO 1 full.

Bit 5 – RF1W: Rx FIFO 1 Watermark Reached

Rx FIFO 1 Watermark Reached

ValueDescription
0 Rx FIFO 1 fill level below watermark.
1 Rx FIFO 1 fill level reached watermark.

Bit 4 – RF1N: Rx FIFO 1 New Message

Rx FIFO 1 New Message

ValueDescription
0 No new message written to Rx FIFO 1.
1 New message written to Rx FIFO 1.

Bit 3 – RF0L: Rx FIFO 0 Message Lost

Rx FIFO 0 Message Lost

ValueDescription
0 No Rx FIFO 0 message lost.
1 Rx FIFO 0 message lost. also set after write attempt to Rx FIFO 0 of size zero.

Bit 2 – RF0F: Rx FIFO 0 Full

Rx FIFO 0 Full

ValueDescription
0 Rx FIFO 0 not full.
1 Rx FIFO 0 full.

Bit 1 – RF0W: Rx FIFO 0 Watermark Reached

Rx FIFO 0 Watermark Reached

ValueDescription
0 Rx FIFO 0 fill level below watermark.
1 Rx FIFO 0 fill level reached watermark.

Bit 0 – RF0N: Rx FIFO 0 New Message

Rx FIFO 0 New Message

ValueDescription
0 No new message written to Rx FIFO 0.
1 New message written to Rx FIFO 0.