| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DBGRUN | |||||||
| Access | R/W | ||||||
| Reset | 0 |
Debug Run
This bit is not reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
This bit should be written only while a conversion is not ongoing.
| Value | Description |
|---|---|
| 0 | The SDADC is halted when the CPU is halted by an external debugger. |
| 1 | The SDADC continues normal operation when the CPU is halted by an external debugger. |