Figure 1. Master-Slave Relation High-Speed Bus
Matrix
| Bus Matrix Masters | Master ID |
|---|---|
| CM0+ - Cortex M0+ Processor | 0 |
| DSU - Device Service Unit | 1 |
| DMAC - Direct Memory Access Controller / Data Access | 2 |
| Bus Matrix Slaves | Slave ID |
|---|---|
| Internal Flash Memory | 0 |
| SRAM Port 4 - CM0+ Access | 1 |
| SRAM Port 6 - DSU Access | 2 |
| AHB-APB Bridge A | 3 |
| AHB-APB Bridge B | 4 |
| AHB-APB Bridge C | 5 |
| SRAM Port 5 - DMAC Data Access | 6 |
| DIVAS - Divide Accelerator | 7 |
| SRAM Port Connection | Port ID | Connection Type |
|---|---|---|
| CM0+ - Cortex M0+ Processor | 0 | Bus Matrix |
| DSU - Device Service Unit | 1 | Bus Matrix |
| DMAC - Direct Memory Access Controller - Data Access | 2 | Bus Matrix |
| DMAC - Direct Memory Access Controller - Fetch Access 0 | 3 | Direct |
| DMAC - Direct Memory Access Controller - Fetch Access 1 | 4 | Direct |
| DMAC - Direct Memory Access Controller - Write-Back Access 0 | 5 | Direct |
| DMAC - Direct Memory Access Controller - Write-Back Access 1 | 6 | Direct |
|
CAN0 - Controller Area Network 0 |
7 | Direct |
|
CAN1 - Controller Area Network 1 |
8 | Direct |
| MTB - Micro Trace Buffer | 9 | Direct |