| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| Access | |||||||
| Reset | |||||||
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Access | |||||||
| Reset | |||||||
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Access | |||||||
| Reset | |||||||
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ENABLE | SWRST | ||||||
| Access | R | R | |||||
| Reset | 0 | 0 |
Enable Busy
This bit is cleared when the synchronization of CTRLA.ENABLE is complete.
This bit is set when the synchronization of CTRLA.ENABLE is started.
Software Reset Busy
This bit is cleared when the synchronization of CTRLA.SWRST is complete.
This bit is set when the synchronization of CTRLA.SWRST is started.