Protocol Status
Note:
  1. When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in FLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error.
  2. The Bus_Off recovery sequence (see CAN Specification Rev. 2.0 or ISO 11898-1) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0 Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences.
Name:
PSR
Offset:
0x44
Reset:
0x00000707
Access:
Read-only
Bit3130292827262524
Access
Reset
Bit2322212019181716
TDCV[6:0]
AccessRRRRRRR
Reset0000000
Bit15141312111098
PXERFDFRBRSRESIDLEC[2:0]
AccessRRRRRRR
Reset0000111
Bit76543210
BOEWEPACT[1:0]LEC[2:0]
AccessRRRRRRRR
Reset00000111

Bits 22:16 – TDCV[6:0]: Transmitter Delay Compensation Value

Transmitter Delay Compensation Value

ValueDescription
0x00 - 0x7F Position of the secondary sample point, defined by the sum of the measured delay from CAN_TX to CAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.

Bit 14 – PXE: Protocol Exception Event

Protocol Exception Event

This field is cleared on read access.
ValueDescription
0 No protocol exception event occurred since last read access.
1 Protocol exception event occurred.

Bit 13 – RFDF: Received a CAN FD Message

Received a CAN FD Message

This field is cleared on read access.
ValueDescription
0 Since this bit was reset by the CPU, no CAN FD message has been received.
1 Message in CAN FD format with FDF flag set has been received. This bit is set independent of acceptance filtering.

Bit 12 – RBRS: BRS flag of last received CAN FD Message

BRS flag of last received CAN FD Message

This field is cleared on read access.
ValueDescription
0 Last received CAN FD message did not have its BRS flag set.
1 Last received CAN FD message had its BRS flag set. This bit is set together with RFDF, independent of acceptance filtering.

Bit 11 – RESI: ESI flag of last received CAN FD Message

ESI flag of last received CAN FD Message

This field is cleared on read access.
ValueDescription
0 Last received CAN FD message did not have its ESI flag set.
1 Last received CAN FD message had its ESI flag set.

Bits 10:8 – DLEC[2:0]: Data Last Error Code

Data Last Error Code

Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.

Bit 7 – BO: Bus_Off Status

Bus_Off Status

ValueDescription
0 The CAN is not Bus_Off.
1 The CAN is in Bus_Off state.

Bit 6 – EW: Error Warning Status

Error Warning Status

ValueDescription
0 Both error counters are below the Error_Warning limit of 96.
1 At least one of the error counter has reached the Error_Warning limit of 96.

Bit 5 – EP: Error Passive

Error Passive

ValueDescription
0 The CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected.
1 The CAN is in the Error_Passive state.

Bits 4:3 – ACT[1:0]: Activity

Activity

Monitors the module’s CAN communication state.
ValueNameDescription
0x0 SYNC Node is synchronizing on CAN communication.
0x1 IDLE Node is neither receiver nor transmitter.
0x2 RX Node is operating as receiver.
0x3 TX Node is operating as transmitter.

Bits 2:0 – LEC[2:0]: Last Error Code

Last Error Code

The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’ when a message has been transferred (reception or transmission) without error.

This field is set on read access.

ValueNameDescription
0x0 NONE No Error: No error occurred since LEC has been reset by successful reception or transmission.
0x1 STUFF Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
0x2 FORM Form Error: A fixed format part of a received frame has the wrong format.
0x3 ACK Ack Error: The message transmitted by the CAN was not acknowledged by another node.
0x4 BIT1 Bit1 Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus was dominant.
0x5 BIT0 Bit0 Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value ‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits have been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
0x6 CRC CRC Error: The CRC checksum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.
0x7 NC No Change: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register.