Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x04
Reset:
0x00
Access:
PAC Write-Protection
Bit76543210
EMPTYUNDERRUN
AccessR/WR/W
Reset00

Bit 1 – EMPTY: Data Buffer Empty Interrupt Enable

Data Buffer Empty Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Data Buffer Empty Interrupt Enable bit, which disables the Data Buffer Empty interrupt.

ValueDescription
0 The Data Buffer Empty interrupt is disabled.
1 The Data Buffer Empty interrupt is enabled.

Bit 0 – UNDERRUN: Underrun Interrupt Enable

Underrun Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Data Buffer Underrun Interrupt Enable bit, which disables the Data Buffer Underrun interrupt.

ValueDescription
0 The Data Buffer Underrun interrupt is disabled.
1 The Data Buffer Underrun interrupt is enabled.