| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ONDEMAND | RUNSTDBY | ENABLE | SWRST | ||||
| AccessR/W | R/W | R/W | R/W | ||||
| Reset0 | 0 | 0 | 0 |
On Demand Control
The On Demand operation modes allows the SDADC to be enabled or disabled, depending on other peripheral request.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the SDADC will only be running when requested by a peripheral. If there is no peripheral requesting the SDADC will be in a disable state.
If On Demand is disable the SDADC will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the CTRLA.RUNSTDBY bit is one. If CTRLA.RUNSTDBY is zero, the SDADC is disabled.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | The SDADC is always on , if enabled. |
| 1 | The SDADC is enabled, when a peripheral is requesting the SDADC conversion. The SDADC is disabled if no peripheral is requesting it. |
Run in Standby
This bit controls how the SDADC behaves during standby sleep mode:
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | The SDADC is halted during standby sleep mode. |
| 1 | The SDADC is not stopped in standby sleep mode. If CTRLA.ONDEMAND is one, the SDADC will be running when a peripheral is requesting it. If CTRLA.ONDEMAND is zero, the SDADC will always be running in standby sleep mode. |
Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
| Value | Description |
|---|---|
| 0 | The SDADC is disabled. |
| 1 | The SDADC is enabled. |
Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the SDADC, except SYNCBUSY , to their initial state, and the SDADC will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
| Value | Description |
|---|---|
| 0 | There is no reset operation ongoing. |
| 1 | The reset operation is ongoing. |