| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TOP[15:8] | |||||||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TOP[7:0] | |||||||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Access | |||||||
| Reset | |||||||
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TOS[1:0] | ETOC | ||||||
| Access | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | ||||
Timeout Period
Timeout Select
| Value | Name | Description |
|---|---|---|
| 0x0 | CONT | Continuous operation. |
| 0x1 | TXEF | Timeout controlled by TX Event FIFO. |
| 0x2 | RXF0 | Timeout controlled by Rx FIFO 0. |
| 0x3 | RXF1 | Timeout controlled by Rx FIFO 1. |
Enable Timeout Counter
| Value | Description |
|---|---|
| 0 | Timeout Counter disabled. |
| 1 | Timeout Counter enabled. |