Master - Slave Operation

The master - slave operation is available only on devices with two ADC instances. The ADC1 will be enabled as a slave of ADC0 instance when writing a one to the Slave Enable bit in Control A register of the ADC1 instance (ADC1.CTRLA.SLAVEEN). When enabled, GCLK_ADC0 clock and ADC0 controls are internally routed to the ADC1 instance.

Figure 1. ADC Master - Slave Block Diagram

In this mode of operation, the slave ADC is enabled by accessing the CTRLA register of master ADC. In the same way, the master ADC event inputs will be automatically routed to the slave ADC, meaning that the input events configuration must be done in the master ADC (ADC0.EVCTRL).

ADC measurements can be started simultaneously on both ADC’s or interleaved. The trigger mode selection is available in the master ADC Control C register (ADC0.CTRLC.DUALSEL).

Figure 2. Interleaved Dual-Mode Trigger Selection