Multiplexed Signals

Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G, H or I. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.

Table 1. PORT Function Multiplexing
  Pin(1)   I/O Pin Supply A       B(2)(3)       C D E F G H I
SAM C21E SAM C21G SAM C21J     EIC REF ADC0 ADC1 AC PTC

DAC

 SDADC SERCOM(2)(3)(4) SERCOM-ALT(4)

TC

TCC

 TCC COM AC/GCLK CCL
1 1 1 PA00 VDDANA EXTINT[0]                 SERCOM1/
PAD[0] TCC2/WO[0]     CMP[2]  
2 2 2 PA01 VDDANA EXTINT[1]                 SERCOM1/
PAD[1] TCC2/WO[1]     CMP[3]  
3 3 3 PA02 VDDANA EXTINT[2]   AIN[0]   AIN[4] Y[0] VOUT                
4 4 4 PA03 VDDANA EXTINT[3] ADC/VREFA
DAC/VREFA AIN[1]   AIN[5] Y[1]                  
    5 PB04 VDDANA EXTINT[4]    

AIN[6]

   Y[10]                  
    6 PB05 VDDANA EXTINT[5]    

AIN[7]

 AIN[6] Y[11]                  
    9 PB06 VDDANA EXTINT[6]    

AIN[8]

 AIN[7] Y[12]  

INN[2]

             CCL2/

IN[6]
    10 PB07 VDDANA EXTINT[7]    

AIN[9]

   Y[13]  

INP[2]

             CCL2/

IN[7]
  7 11 PB08 VDDANA EXTINT[8]   AIN[2]

AIN[4]

   Y[14]  

INN[1]

   SERCOM4/
PAD[0] TC0/WO[0]       CCL2/

IN[8]
  8 12 PB09 VDDANA EXTINT[9]   AIN[3]

AIN[5]

   Y[15]  

INP[1]

   SERCOM4/
PAD[1] TC0WO[1]       CCL2/

OUT[2]
5 9 13 PA04 VDDANA EXTINT[4] SDADC VREFB AIN[4]   AIN[0] Y[2]       SERCOM0/
PAD[0] TCC0/WO[0]       CCL0/

IN[0]
6 10 14 PA05 VDDANA EXTINT[5]   AIN[5]   AIN[1] Y[3]       SERCOM0/
PAD[1] TCC0/WO[1]       CCL0/

IN[1]
7 11 15 PA06 VDDANA EXTINT[6]   AIN[6]   AIN[2] Y[4]  

INN[0]

   SERCOM0/
PAD[2] TCC1/WO[0]       CCL0/

IN[2]
8 12 16 PA07 VDDANA EXTINT[7]   AIN[7]   AIN[3] Y[5]  

INP[0]

   SERCOM0/
PAD[3] TCC1/WO[1]       CCL0/

OUT[0]
11 13 17 PA08 VDDIO NMI   AIN[8]

AIN[10]

   X[0]/Y[16]     SERCOM0/
PAD[0] SERCOM2/
PAD[0] TCC0/WO[0] TCC1/
WO[2]     CCL1/

IN[3]
12 14 18 PA09 VDDIO EXTINT[9]   AIN[9]

AIN[11]

   X[1]/Y[17]     SERCOM0/
PAD[1] SERCOM2/
PAD[1] TCC0/WO[1] TCC1/
WO[3]     CCL1/

IN[4]
13 15 19 PA10 VDDIO EXTINT[10]   AIN[10]     X[2]/Y[18]     SERCOM0/
PAD[2] SERCOM2/
PAD[2] TCC1/WO[0] TCC0/
WO[2]   GCLK_IO[4] CCL1/

IN[5]
14 16 20 PA11 VDDIO EXTINT[11]   AIN[11]     X[3]/Y[19]     SERCOM0/
PAD[3] SERCOM2/
PAD[3] TCC1/WO[1] TCC0/
WO[3]   GCLK_IO[5] CCL1/

OUT[1]
  19 23 PB10 VDDIO EXTINT[10]                 SERCOM4/
PAD[2] TC1/WO[0] TCC0/
WO[4]

CAN1/TX

 GCLK_IO[4] CCL1/

IN[5]
  20 24 PB11 VDDIO EXTINT[11]                 SERCOM4/
PAD[3] TC1/WO[1] TCC0/
WO[5]

CAN1/RX

 GCLK_IO[5] CCL1/

OUT[1]
    25 PB12 VDDIO EXTINT[12]         X[12]/Y[28]     SERCOM4/
PAD[0]   TC0/WO[0] TCC0/
WO[6]   GCLK_IO[6]  
    26 PB13 VDDIO EXTINT[13]         X[13]/Y[29]     SERCOM4/
PAD[1]   TC0/WO[1] TCC0/
WO[7]   GCLK_IO[7]  
    27 PB14 VDDIO EXTINT[14]         X[14]/Y[30]     SERCOM4/
PAD[2]   TC1/WO[0]  

CAN1/TX

 GCLK_IO[0] CCL3/

IN[9]
    28 PB15 VDDIO EXTINT[15]         X[15]/Y[31]     SERCOM4/
PAD[3]   TC1/WO[1]  

CAN1/RX

 GCLK_IO[1] CCL3/

IN[10]
  21 29 PA12 VDDIO EXTINT[12]               SERCOM2/
PAD[0] SERCOM4/
PAD[0] TCC2/WO[0] TCC0/
WO[6]   AC/CMP[0]  
  22 30 PA13 VDDIO EXTINT[13]               SERCOM2/
PAD[1] SERCOM4/
PAD[1] TCC2/WO[1] TCC0/
WO[7]   AC/CMP[1]  
15 23 31 PA14 VDDIO EXTINT[14]               SERCOM2/
PAD[2] SERCOM4/
PAD[2] TC4/WO[0] TCC0/
WO[4]   GCLK_IO[0]  
16 24 32 PA15 VDDIO EXTINT[15]               SERCOM2/
PAD[3] SERCOM4/
PAD[3] TC4/WO[1] TCC0/
WO[5]   GCLK_IO[1]  
17 25 35 PA16 VDDIO EXTINT[0]         X[4]/Y[20]     SERCOM1/
PAD[0] SERCOM3/
PAD[0] TCC2/WO[0] TCC0/
WO[6]   GCLK_IO[2] CCL0/

IN[0]
18 26 36 PA17 VDDIO EXTINT[1]         X[5]/Y[21]     SERCOM1/
PAD[1] SERCOM3/
PAD[1] TCC2/WO[1] TCC0/
WO[7]   GCLK_IO[3] CCL0/

IN[1]
19 27 37 PA18 VDDIO EXTINT[2]         X[6]/Y[22]     SERCOM1/
PAD[2] SERCOM3/
PAD[2] TC4/WO[0] TCC0/
WO[2]   AC/CMP[0] CCL0/

IN[2]
20 28 38 PA19 VDDIO EXTINT[3]         X[7]/Y[23]     SERCOM1/
PAD[3] SERCOM3/
PAD[3] TC4/WO[1] TCC0/
WO[3]   AC/CMP[1] CCL0/

OUT[0]
    39 PB16 VDDIO EXTINT[0]               SERCOM5/
PAD[0]   TC2/WO[0] TCC0/
WO[4]   GCLK_IO[2] CCL3/

IN[11]
    40 PB17 VDDIO EXTINT[1]               SERCOM5/
PAD[1]   TC2/WO[1] TCC0/
WO[5]   GCLK_IO[3] CCL3/

OUT[3]
  29 41 PA20 VDDIO EXTINT[4]         X[8]/Y[24]     SERCOM5/
PAD[2] SERCOM3/
PAD[2] TC3/WO[0] TCC0/
WO[6]   GCLK_IO[4]  
  30 42 PA21 VDDIO EXTINT[5]         X[9]/Y[25]     SERCOM5/
PAD[3] SERCOM3/
PAD[3] TC3/WO[1] TCC0/
WO[7]   GCLK_IO[5]  
21 31 43 PA22 VDDIO EXTINT[6]         X[10]/Y[26]     SERCOM3/
PAD[0] SERCOM5/
PAD[0] TC0/WO[0] TCC0/
WO[4]   GCLK_IO[6] CCL2/

IN[6]
22 32 44 PA23 VDDIO EXTINT[7]         X[11]/Y[27]     SERCOM3/
PAD[1] SERCOM5/
PAD[1] TC0/WO[1] TCC0/
WO[5]   GCLK_IO[7] CCL2/

IN[7]
23 33 45 PA24 VDDIO EXTINT[12]               SERCOM3/
PAD[2] SERCOM5/
PAD[2] TC1/WO[0] TCC1/
WO[2]

CAN0/TX

 AC/CMP[2] CCL2/

IN[8]
24 34 46 PA25 VDDIO EXTINT[13]               SERCOM3/
PAD[3] SERCOM5/
PAD[3] TC1/WO[1] TCC1/
WO[3]

CAN0/RX

 AC/CMP[3] CCL2/

OUT[2]
  37 49 PB22 VDDIN EXTINT[6]                 SERCOM5/
PAD[2] TC3/WO[0]  

CAN0/TX

 GCLK_IO[0] CCL0/

IN[0]
  38 50 PB23 VDDIN EXTINT[7]                 SERCOM5/
PAD[3] TC3/WO[1]  

CAN0/RX

 GCLK_IO[1] CCL0/

OUT[0]
25 39 51 PA27 VDDIN EXTINT[15]                       BRK GCLK_IO[0]  
27 41 53 PA28 VDDIN EXTINT[8]                         GCLK_IO[0]  
31 45 57 PA30 VDDIN EXTINT[10]                 SERCOM1/
PAD[2] TCC1/WO[0]   CORTEX_M0P/
SWCLK GCLK_IO[0] CCL1/

IN[3]
32 46 58 PA31 VDDIN EXTINT[11]                 SERCOM1/
PAD[3] TCC1/WO[1]   CORTEX_M0P/
SWDIO   CCL1/

OUT[1]
    59 PB30 VDDIN EXTINT[14]                 SERCOM5/
PAD[0] TCC0/WO[0] TCC1/
WO[2]   AC/CMP[2]  
    60 PB31 VDDIN EXTINT[15]                 SERCOM5/
PAD[1] TCC0/WO[1] TCC1/
WO[3]   AC/CMP[3]  
    61 PB00 VDDANA EXTINT[0]    

AIN[0]

   Y[6]       SERCOM5/
PAD[2] TC3/WO[0]       CCL0/

IN[1]
    62 PB01 VDDANA EXTINT[1]    

AIN[1]

   Y[7]       SERCOM5/
PAD[3] TC3/WO[1]       CCL0/

IN[2]
  47 63 PB02 VDDANA EXTINT[2]    

AIN[2]

   Y[8]       SERCOM5/
PAD[0] TC2/WO[0]       CCL0/

OUT[0]
  48 64 PB03 VDDANA EXTINT[3]    

AIN[3]

   Y[9]       SERCOM5/
PAD[1] TC2/WO[1]        
  1. Use the SAM C21J pinout muxing for the WLCSP56 package.

  2. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin.

  3. Only some pins can be used in SERCOM I2C mode. Refer to SERCOM I2C Pins.

  4. SERCOM4 and SERCOM5 are not supported on SAM C21E

Parent topic: I/O Multiplexing and Considerations
Related information
SERCOM I2C Pins