Rx FIFO 1 Status
Name:
RXF1S
Offset:
0xB4
Reset:
0x00000000
Access:
Read-only
Bit3130292827262524
DMS[1:0]RF1LF1F
AccessRRRR
Reset0000
Bit2322212019181716
F1PI[5:0]
AccessRRRRRR
Reset000000
Bit15141312111098
F1GI[5:0]
AccessRRRRRR
Reset000000
Bit76543210
F1FL[6:0]
AccessRRRRRRR
Reset0000000

Bits 31:30 – DMS[1:0]: Debug Message Status

Debug Message Status

This field defines the debug message status.

ValueNameDescription
0x0 IDLE Idle state, wait for reception of debug messages, DMA request is cleared.
0x1 DBGA Debug message A received.
0x2 DBGB Debug message A, B received.
0x3 DBGC Debug message A, B, C received, DMA request is set.

Bit 25 – RF1L: Rx FIFO 1 Message Lost

Rx FIFO 1 Message Lost

This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset.

Overwriting the oldest message when RXF1C.F0OM = ‘1’ will not set this flag.

ValueDescription
0 No Rx FIFO 1 message lost.
1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero.

Bit 24 – F1F: Rx FIFO 1 Full

Rx FIFO 1 Full

ValueDescription
0 Rx FIFO 1 not full.
1 Rx FIFO 1 full.

Bits 21:16 – F1PI[5:0]: Rx FIFO 1 Put Index

Rx FIFO 1 Put Index

Rx FIFO 1 write index pointer, range 0 to 63.

Bits 13:8 – F1GI[5:0]: Rx FIFO 1 Get Index

Rx FIFO 1 Get Index

Rx FIFO 1 read index pointer, range 0 to 63.

Bits 6:0 – F1FL[6:0]: Rx FIFO 1 Fill Level

Rx FIFO 1 Fill Level

Number of elements stored in Rx FIFO 1, range 0 to 64.