Up to 64 filter elements can be configured for 29-bit extended IDs. When accessing an Extended Message ID Filter element, its address is the Filter List Extended Start Address XIDFC.FLESA plus two times the index of the filter element (0…63).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | EFEC [2:0] |
EFID1[28:0] | ||||||||||||||||||||||||||||||
| F1 | EFT [1:0] |
EFID2[28:0] | ||||||||||||||||||||||||||||||
F0 Bits 31:29 - EFEC[2:0]: Extended Filter Element Configuration
All enabled filter elements are used for acceptance filtering of extended frames. Acceptance filtering stops at the first matching enabled filter element or when the end of the filter list is reached. If EFEC = “100”, “101”, or “110” a match sets interrupt flag IR.HPM and, if enabled, an interrupt is generated. In this case register HPMS is updated with the status of the priority match.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Disable filter element. |
| 0x1 | STF0M | Store in Rx FIFO 0 if filter matches. |
| 0x2 | STF1M | Store in Rx FIFO 1 if filter matches. |
| 0x3 | REJECT | Reject ID if filter matches. |
| 0x4 | PRIORITY | Set priority if filter matches. |
| 0x5 | PRIF0M | Set priority and store in FIFO 0 if filter matches. |
| 0x6 | PRIF1M | Set priority and store in FIFO 1 if filter matches. |
| 0x7 | STRXBUF | Store into Rx Buffer or as debug message, configuration of EFT[1:0] ignored. |
F0 Bits 28:0 - EFID1[28:0]: Extended Filter ID 1
First ID of extended ID filter element.
When filtering for Rx Buffers or for debug messages this field defines the ID of a extended mesage to be stored. The received identifiers must match exactly, only XIDAM masking mechanism is used.
F1 Bits 31:30 - EFT[1:0]: Extended Filter Type
This field defines the extended filter type.
| Value | Name | Description |
|---|---|---|
| 0x0 | RANGEM | Range filter from EFID1 to EFID2 (EFID2 >= EFID1). |
| 0x1 | DUAL | Dual ID filter for EFID1 or EFID2. |
| 0x2 | CLASSIC | Classic filter: EFID1 = filter, EFID2 = mask. |
| 0x3 | RANGE | Range filter from EFID1 to EFID2 (EFID2 >= EFID1), XIDAM mask not applied. |
F1 Bits 28:0 - EFID2[28:0]: Extended Filter ID 2
This bit field has a different meaning depending on the configuration of EFEC. 1) EFEC = “001” ... “110” Second ID of standard ID filter element. 2) EFEC = “111” Filter for Rx Buffers or for debug messages.
EFID2[10:9] decides whether the received message is stored into an Rx Buffer or treated as message A, B, or C of the debug message sequence.
00 = Store message into an Rx Buffer
01 = Debug Message A
10 = Debug Message B
11 = Debug Message C
EFID2[8:6] is used to control the filter event pins at the Extension Interface. A ‘1’ at the respective bit position enables generation of a pulse at the related filter event pin with the duration of one CLK_CAN_APB period in case the filter matches.
EFID2[5:0] defines the offset to the Rx Buffer Start Address RXBC.RBSA for storage of a matching message.