ECR

Error Counter

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TECand REC when a CAN protocol error is detected, but CEL is still incremented.

Name:: ECR
Offset:: 0x40
Reset:: 0x00000000
Access:: Read-only

Bit31	30	29	28	27	26	25	24

Access
Reset
Bit23	22	21	20	19	18	17	16
CEL[7:0]
AccessR	R	R	R	R	R	R	R
Reset0	0	0	0	0	0	0	0
Bit15	14	13	12	11	10	9	8
RP	REC[6:0]
AccessR	R	R	R	R	R	R	R
Reset0	0	0	0	0	0	0	0
Bit7	6	5	4	3	2	1	0
TEC[7:0]
AccessR	R	R	R	R	R	R	R
Reset0	0	0	0	0	0	0	0

Bits 23:16 – CEL[7:0]: CAN Error Logging

CAN Error Logging

The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO.

Bit 15 – RP: Receive Error Passive

Receive Error Passive

Bits 14:8 – REC[6:0]: Receive Error Counter

Receive Error Counter

Actual state of the Receive Error Counter, values between 0 and 127.

Bits 7:0 – TEC[7:0]: Transmit Error Counter

Transmit Error Counter

Actual state of the Transmit Error Counter, values between 0 and 255.