Tx Event FIFO Status
Name:
TXEFS
Offset:
0xF4
Reset:
0x00000000
Access:
Read-only
Bit3130292827262524
TEFLEFF
AccessRR
Reset00
Bit2322212019181716
EFP[4:0]
AccessRRRRR
Reset00000
Bit15141312111098
EFGI[4:0]
AccessRRRRR
Reset00000
Bit76543210
EFFI[4:0]
AccessRRRRR
Reset00000

Bit 25 – TEFL: Tx Event FIFO Element Lost

Tx Event FIFO Element Lost

This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset.

ValueDescription
0 No Tx Event FIFO element lost.
1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.

Bit 24 – EFF: Event FIFO Full

Event FIFO Full

ValueDescription
0 Tx Event FIFO not full.
1 Tx Event FIFO full.

Bits 20:16 – EFP[4:0]: Event FIFO Put Index

Event FIFO Put Index

Tx Event FIFO write index pointer, range 0 to 31.

Bits 12:8 – EFGI[4:0]: Event FIFO Get Index

Event FIFO Get Index

Tx Event FIFO read index pointer, range 0 to 31.

Bits 4:0 – EFFI[4:0]: Event FIFO Fill Level

Event FIFO Fill Level

Number of elements stored in Tx Event FIFO, range 0 to 32.