BASEADDR

Descriptor Memory Section Base Address

Name:: BASEADDR
Offset:: 0x34
Reset:: 0x00000000
Access:: PAC Write-Protection, Enable-Protected

Bit31	30	29	28	27	26	25	24
BASEADDR[31:24]
AccessR/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset0	0	0	0	0	0	0	0
Bit23	22	21	20	19	18	17	16
BASEADDR[23:16]
AccessR/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset0	0	0	0	0	0	0	0
Bit15	14	13	12	11	10	9	8
BASEADDR[15:8]
AccessR/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset0	0	0	0	0	0	0	0
Bit7	6	5	4	3	2	1	0
BASEADDR[7:0]
AccessR/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset0	0	0	0	0	0	0	0

Bits 31:0 – BASEADDR[31:0]: Descriptor Memory Base Address

Descriptor Memory Base Address

These bits store the Descriptor memory section base address. The value must be 128-bit aligned.