WAVEB

Name:: WAVEB
Offset:: 0x68
Reset:: 0x00000000
Access:: Write-Synchronized, Read-Synchronized

Bit31	30	29	28	27	26	25	24
				SWAPB 3	SWAPB 2	SWAPB 1	SWAPB 0
Access				R/W	R/W	R/W	R/W
Reset				0	0	0	0
Bit23	22	21	20	19	18	17	16
				POLB3	POLB2	POLB1	POLB0
Access				R/W	R/W	R/W	R/W
Reset				0	0	0	0
Bit15	14	13	12	11	10	9	8
				CICCENB3	CICCENB2	CICCENB1	CICCENB0
Access				R/W	R/W	R/W	R/W
Reset				0	0	0	0
Bit7	6	5	4	3	2	1	0
CIPERENB		RAMPB[1:0]			WAVEGENB[2:0]
AccessR/W		R/W	R/W		R/W	R/W	R/W
Reset0		0	0		0	0	0

Bit 7 – CIPERENB: Circular Period Enable Buffer

Circular Period Enable Buffer

This register bit is the buffer bit for CIPEREN register bit. If double buffering is used, valid content in this bit is copied to the corresponding CIPEREN bit on a UPDATE condition.

Bits 5:4 – RAMPB[1:0]: Ramp Operation Buffer

Ramp Operation Buffer

These register bits are the buffer bits for RAMP register bits. If double buffering is used, valid content in these bits is copied to the corresponding RAMP bits on a UPDATE condition.

Bits 2:0 – WAVEGENB[2:0]: Waveform Generation Operation Buffer

Waveform Generation Operation Buffer

These register bits are the buffer bits for WAVEGEN register bits. If double buffering is used, valid content in these bits is copied to the corresponding WAVEGEN bits on a UPDATE condition.

Bits 24, 25, 26, 27 – SWAPB n: Swap DTI output pair x Buffer

Swap DTI output pair x Buffer

These register bits are the buffer bits for the SWAP register bits. If double buffering is used, valid content in these bits is copied to the corresponding SWAPx bits on an UPDATE condition.

Bits 16, 17, 18, 19 – POLBn: Channel Polarity x Buffer

Channel Polarity x Buffer

These register bits are the buffer bits for POLx register bits. If double buffering is used, valid content in these bits is copied to the corresponding POBx bits on an UPDATE condition.

Bits 8, 9, 10, 11 – CICCENBn: Circular CCx Buffer Enable

Circular CCx Buffer Enable

These register bits are the buffer bits for CICCENx register bits. If double buffering is used, valid content in these bits is copied to the corresponding CICCENx bits on a UPDATE condition.