PER

Name:: PER
Offset:: 0x40
Reset:: 0xFFFFFFFF
Access:: Write-Synchronized

Bit31	30	29	28	27	26	25	24

Access
Reset
Bit23	22	21	20	19	18	17	16
PER[17:10]
AccessR/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset1	1	1	1	1	1	1	1
Bit15	14	13	12	11	10	9	8
PER[9:2]
AccessR/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset1	1	1	1	1	1	1	1
Bit7	6	5	4	3	2	1	0
PER[1:0]		DITHER[5:0]
AccessR/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset1	1	1	1	1	1	1	1

Bits 23:6 – PER[17:0]: Period Value

Period Value

These bits hold the value of the period buffer register.

Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.

Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION	Bits [23:m]
0x0 - NONE	23:0
0x1 - DITH4	23:4
0x2 - DITH5	23:5
0x3 - DITH6	23:6 (depicted)

Bits 5:0 – DITHER[5:0]: Dithering Cycle Number

Dithering Cycle Number

These bits hold the number of extra cycles that are added on the PWM pulse period every 64 PWM frames.

Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION	Bits [n:0]
0x0 - NONE	-
0x1 - DITH4	3:0
0x2 - DITH5	4:0
0x3 - DITH6	5:0 (depicted)