INTFLAG

Interrupt Flag Status and Clear

Name:: INTFLAG
Offset:: 0x08
Reset:: 0x00000000
Access:: -

Bit31	30	29	28	27	26	25	24

Access
Reset
Bit23	22	21	20	19	18	17	16

Access
Reset
Bit15	14	13	12	11	10	9	8
				DPLLLDRTO	DPLLLTO	DPLLLCKF	DPLLLCKR
Access				R/W	R/W	R/W	R/W
Reset				0	0	0	0
Bit7	6	5	4	3	2	1	0
			OSC48MRDY			CLKFAIL	XOSCRDY
Access			R/W			R/W	R/W
Reset			0			0	0

Bit 11 – DPLLLDRTO: DPLL Loop Divider Ratio Update Complete

DPLL Loop Divider Ratio Update Complete

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DPLL Loop Divider Ratio Update Complete bit in the Status register (STATUS.DPLLLDRTO) and will generate an interrupt request if INTENSET.DPLLLDRTO is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DPLL Loop Divider Ratio Update Complete interrupt flag.

Bit 10 – DPLLLTO: DPLL Lock Timeout

DPLL Lock Timeout

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DPLL Lock Timeout bit in the Status register (STATUS.DPLLLTO) and will generate an interrupt request if INTENSET.DPLLLTO is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DPLL Lock Timeout interrupt flag.

Bit 9 – DPLLLCKF: DPLL Lock Fall

DPLL Lock Fall

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DPLL Lock Fall bit in the Status register (STATUS.DPLLLCKF) and will generate an interrupt request if INTENSET.DPLLLCKF is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DPLL Lock Fall interrupt flag.

Bit 8 – DPLLLCKR: DPLL Lock Rise

DPLL Lock Rise

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DPLL Lock Rise bit in the Status register (STATUS.DPLLLCKR) and will generate an interrupt request if INTENSET.DPLLLCKR is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DPLL Lock Rise interrupt flag.

Bit 4 – OSC48MRDY: OSC48M Ready

OSC48M Ready

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the OSC48M Ready bit in the Status register (STATUS.OSC48MRDY) and will generate an interrupt request if INTENSET.OSC48MRDY is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the OSC48M Ready interrupt flag.

Bit 1 – CLKFAIL: XOSC Failure Detection

XOSC Failure Detection

This flag is cleared by writing '1' to it.

This flag is set on a 0-to-1 transition of the XOSC Clock Failure bit in the Status register (STATUS.CLKFAIL) and will generate an interrupt request if INTENSET.CLKFAIL is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the XOSC Clock Fail interrupt flag.

Bit 0 – XOSCRDY: XOSC Ready

XOSC Ready

This flag is cleared by writing '1' to it.

This flag is set on a 0-to-1 transition of the XOSC Ready bit in the Status register (STATUS.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the XOSC Ready interrupt flag.