Errata

The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die.

Die Revision B

OSC48M

  1. When a System Reset is applied, the OSC48MDIV register is reset, but the value is not synchronized. This may result in the system clock running too fast.
    Errata reference: 14497
    Fix/Workaround:
    Do not write OSC48MDIV to lower than 0xB.
    Do not run the device faster than 4MHz when running from internal oscillators

PORT

  1. When the PORT is defined as EVSYS.USER in a synch/resynch path, the first event is transmitted to the PORT but the acknowledgement coming from the PORT is not released. So next coming events are treated as overrun by EVSYS.
    Errata reference: 14317
    Fix/Workaround:
    None.
    Do not use the synch/resynch path, only use asynchronous path.

RTC

  1. The COUNTSYNC/CLOCKSYNC bit of the RTC.CTRLA register has no effect. Read synchronization of the COUNT/CLOCK register is always enabled.
    Errata reference: 13714
    Fix/Workaround:
    None

OSC32KCTRL

  1. At start-up and in case of clock failure detection(CFD), the auto switch by the CFD does not work if the XOSC32K is requested by the GCLK.
    Errata/Workaround
    Manually change clock from XOSC32K to another 32K source.

DAC

  1. DAC in dithering mode with right adjust data leads to INL of 16 LSBs.
    Errata reference: 14642
    Fix/Workaround:
    Use dithering with left adjusted data only

Device

  1. The SYSTICK calibration value is incorrect.
    Errata reference: 14156
    Fix/Workaround:
    The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize the Systick RELOAD value register, which should be initialized instead with a value depending on the main clock frequency and on the tick period required by the application. For a detailed description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
  2. In IDLE sleep mode, the APB and AHB clocks are not stopped if the FDPLL is running as a GCLK clock source.
    Errata reference: 13401
    Fix/Workaround:
    Disable the FDPLL before entering IDLE sleep mode.
  3. The Analog Comparators and ADC1 use the same generic clock configuration. GCLK_ADC1 must be used to configure the clock for AC as GCLK_AC is not functional.
    Errata reference: 13404
    Fix/Workaround:
    None
  4. Increased power consumption in standby sleep mode.
    Errata reference: 14100
    Fix/Workaround:
    None
  5. In I2C Slave mode, writing the CTRLB register when in the AMATCH or DRDY interrupt service routines can cause the state machine to reset.
    Errata reference: 13574
    Fix/Workaround:
    Write CTRLB.ACKACT to 0 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Write CTRLB.ACKACT to 1 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close out a transaction.
    When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit position instead of using CTRLB.CMD. The DRDY interrupt is automatically cleared by reading/writing to the DATA register in smart mode. If not in smart mode, DRDY should be cleared by writing a 1 to its bit position.
    Code replacements examples:
    Current:
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Current:
    SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Current:
    /* ACK or NACK address */
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
    Change to:
    // CMD=0x3 clears all interrupts, so to keep the result similar,
    // PREC is cleared if it was set.
    if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
    SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
  6. VREGSMOD bits have no effect in PM.STDBYCFG register. The power domain controller always operates in automatic regulator mode.
    Errata reference: 14498
    Fix/Workaround:
    None
  7. The OSC48M accuracy cannot be reached for the whole VDD range.
    Errata reference: 15342
    Fix/Workaround:
    Rev A / B: none
    Rev C: limited VDD range, according to the Electrical Characteristics chapter
    Rev D: write OSCCTRL.CAL48M register, depending on the VDD range used.
  8. The default TC selection as CCL input is not TC0, but TC4. Thus the TC selection for the CCL is TC4/TC0/TC1/TC2 instead of TC0/TC1/TC2/TC3. The TC alternate selection is TC0/TC1/TC2/TC3 instead of TC1/TC2/TC3/TC4.
    Errata reference: 13449
    Fix/Workaround:
    Use the TC input mapping described above.

FDPLL

  1. When entering standby mode, the FDPLL is still running even if not requested by any module causing extra consumption.
    Errata reference: 12244
    Fix/Workaround:
    FDPLL must be disabled before entering in standby mode and re-enabled after wake-up

DMAC

  1. When using more than one DMA channel and if one of these DMA channels has a linked descriptor, a fetch error can appear on this channel.
    Errata reference: 15670
    Fix/Workaround:
    Do not use linked descriptors, make a software link instead:
    Replace the channel which used linked descriptor by two channels DMA (with linked descriptor disabled) handled by two channels event system:
    - DMA channel 0 transfer completion is able to send a conditional event for DMA channel 1 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 0 and configuration CHCTRLB.EVACT=CBLOCK for channel 1).
    - On the transfer complete reception of the DMA channel 0, immediately re-enable the channel 0.
    - Then DMA channel 1 transfer completion is able to send a conditional event for DMA channel 0 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 1 and configuration CHCTRLB.EVACT=CBLOCK for channel 0).
    - On the transfer complete reception of the DMA channel 1, immediately re-enable the channel 1.
    - The mechanism can be launched by sending a software event on the DMA channel 0.
  2. If data is written to CRCDATAIN in two consecutive instructions, the CRC computation may be incorrect.
    Errata reference: 13507
    Fix/Workaround:
    Add a NOP instruction between each write to CRCDATAIN register.

EIC

  1. The EIC ASYNCH register is not write protected.
    Errata reference: 13848
    Fix/Workaround:
    None
  2. If the NMI pin PORT config is INPUT+PULL-UP enabled and the NMI is configured to trigger on rising edge (or both edges), the NMI exception is triggered as soon as the NMI config is written.
    Errata reference: 13074
    Fix/Workaround:
    Set the NMI pin PORT config, enable EIC in edge detection mode then disable EIC. Clear INTFLAG, then write NMI configuration.
  3. When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit.
    Errata reference: 15278
    Fix/Workaround:
    Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts.

NVMCTRL

  1. The RWW EEPROM cache is not invalidated when performing write or erase operations. Reading RWWEE cached data can result in outdated data.
    Errata reference: 14633
    Fix/Workaround:
    When the RWW EEPROM Cache is on (CTRLB.CACHEDIS=0x2 or CTRLB.CACHEDIS=0x3) invalidate the cache by issuing the INVALL NVMCTRL command immediately after issuing a RWW EEPROM write or erase operation.

EVSYS

  1. The acknowledge between an event user and the EVSYS clears the CHSTATUS.CHBUSYn bit before this information is fully propagated in the EVSYS one GCLK_EVSYS_CHANNEL_n clock cycle later. As a consequence, any generator event occurring on that channel before that extra GCLK_EVSYS_CHANNEL_n clock cycle will trigger the overrun flag.
    Errata reference: 14835
    Fix/Workaround:
    For applications using event generators other than the software event, monitor the OVR flag.
    For applications using the software event generator, wait one GCLK_EVSYS_CHANNEL_n clock cycle after the CHSTATUS.CHBUSYn bit is cleared before issuing a software event.
  2. Using synchronous, spurious overrun can appear with generic clock for the channel always on.
    Errata reference: 14532
    Fix/Workaround:
    - Request the generic clock on demand by setting the CHANNEL.ONDEMAND bit to one.
    - No penalty is introduced.

SERCOM

  1. In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors.
    Errata reference: 13852
    Fix/Workaround:
    None
  2. If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated.
    Errata reference: 13369
    Fix/Workaround:
    Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1.

TC

  1. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15056
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBuf with a new value, the STATUS.xxBUFV flag must be cleared successively two times.
  2. A capture overflow can occur without INTFLAG.ERR being set if a new capture occurs within 3 APB clock periods + 3 generic clock periods after a previous capture.
    Errata reference: 13367
    Fix/Workaround:
    The delay between two capture events must be longer than 3 APB clock periods + 3 generic clock periods.
  3. The input capture on IO pins does not work.
    Errata reference: 14024
    Fix/Workaround:
    Use the input capture through TC event and use the EIC or CCL as event generators.

TCC

  1. FCTRLX.CAPTURE[CAPTMARK] does not work as described in the datasheet. CAPTMARK cannot be used to identify captured values triggered by fault inputs source A or B on the same channel.
    Errata reference: 13316
    Fix/Workaround:
    Use two different channels to timestamp FaultA and FaultB.
  2. A capture overflow can occur without INTFLAG.ERR being set if a new capture occurs within 3 APB clocks + 3 generic Clock periods from a previous capture.
    Errata reference: 13366
    Fix/Workaround:
    The delay between two capture events must be longer than 3 APB clock periods + 3 generic clock periods.
  3. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15057
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBUF with a new value, the STATUS.xxBUFV flag must be cleared successively two times.
  4. Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) doesn’t work if an upper channel is not in one of these mode. Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN, and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
    Errata reference: 14817
    Fix/Workaround:
    Basic capture mode must be set in lower channel and advance capture mode in upper channel.
    Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN, CC[3]=CAPTMAX
    All capture will be done as expected.
  5. When the circular buffer is enabled, an APB clock is requested to update the corresponding APB register. If all masters in the system (CPU, DMA) are disabled, the APB clock is never provided to the TCC, making the circular buffer feature not functional in standby sleep mode.
    Errata reference: 12269
    Fix/Workaround:
    Keep a master enabled in the system (enable DMA, or do not enable standby sleep mode when circular buffer is enabled).
  6. In RAMP 2 mode with Fault keep, qualified and restart:
    If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can have two restarts.
    Errata reference: 13262
    Fix/Workaround:
    Avoid faults few cycles before the end or the beginning of a ramp.

CCL

  1. The reset of the RS latch is not functional. The latch can only be cleared by disabling the LUT.
    Errata reference: 14043
    Fix/Workaround:
    None

AC

  1. Hysteresis is only present for a falling (1->0) transition of the comparator output.
    Errata reference: 13712
    Fix/Workaround:
    None

ADC

  1. Once set, the ADC.SWTRIG.START will not be cleared until the Microcontroller is reset.
    Errata reference: 14094
    Fix/Workaround:
    None
  2. When window monitor is enabled and its output is 0, the ADC GCLK is kept running. Power consumption will be higher than expected in sleep modes
    Errata reference: 14449
    Fix/Workaround:
    None
  3. The LSB of ADC result is stuck at zero, in unipolar mode for 8-bit and 10-bit resolution.
    Errata reference: 14431
    Fix/Workaround:
    Use 12-bit resolution and take only least 8 bits or 10 bits, if necessary.
  4. If a synchronized event is received during an ADC conversion, the ADC will not acknowledge the event, causing a stall of the event channel.
    Errata reference: 14795
    Fix/Workaround:
    When using events with the ADC, only the asynchronous path from the Event System must be used.

SDADC

  1. Poor INL is observed when the SDADC input signal is close to VREF.
    Errata reference: 15084
    Fix/Workaround:
    SDADC Differential Input Voltage Range should be limited to +/- 0.7.VREF (and not +/- VREF).
    SDADC Single-Ended Input Voltage Range should be limited to 0 to 0.7.VREF (and not 0 to VREF).

PTC

  1. The PTC generic clock is always requested during standby when RUNSTDBY is set to one. Power consumption will be higher if the PTC is enabled during standby sleep mode even if no conversion is on-going.
    Errata reference: 14370
    Fix/workaround
    Disable PTC in standby mode to reduce power consumption

Die Revision C

Device

  1. The OSC48M accuracy cannot be reached for the whole VDD range.
    Errata reference: 15342
    Fix/Workaround:
    Rev A / B: none
    Rev C: limited VDD range, according to the Electrical Characteristics chapter
    Rev D: write OSCCTRL.CAL48M register, depending on the VDD range used.

FDPLL96M

  1. The FDPLL96M exhibits high period jitter and is not suitable for accurate clocking. Accurate clocking is limited to 32MHz and below via XOSC.
    Errata reference: 15174
    Fix/Workaround:
    Connect a XTAL of up to 32MHz to XOSC for a high speed accurate clock source. OSC48M may be used for frequencies up to 48MHz when less accuracy is required.

DMAC

  1. When using more than one DMA channel and if one of these DMA channels has a linked descriptor, a fetch error can appear on this channel.
    Errata reference: 15670
    Fix/Workaround:
    Do not use linked descriptors, make a software link instead:
    Replace the channel which used linked descriptor by two channels DMA (with linked descriptor disabled) handled by two channels event system:
    - DMA channel 0 transfer completion is able to send a conditional event for DMA channel 1 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 0 and configuration CHCTRLB.EVACT=CBLOCK for channel 1).
    - On the transfer complete reception of the DMA channel 0, immediately re-enable the channel 0.
    - Then DMA channel 1 transfer completion is able to send a conditional event for DMA channel 0 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 1 and configuration CHCTRLB.EVACT=CBLOCK for channel 0).
    - On the transfer complete reception of the DMA channel 1, immediately re-enable the channel 1.
    - The mechanism can be launched by sending a software event on the DMA channel 0.

EIC

  1. When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit.
    Errata reference: 15278
    Fix/Workaround:
    Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts.

NVMCTRL

  1. The RWW EEPROM cache is not invalidated when performing write or erase operations. Reading RWWEE cached data can result in outdated data.
    Errata reference: 14633
    Fix/Workaround:
    When the RWW EEPROM Cache is on (CTRLB.CACHEDIS=0x2 or CTRLB.CACHEDIS=0x3) invalidate the cache by issuing the INVALL NVMCTRL command immediately after issuing a RWW EEPROM write or erase operation.

EVSYS

  1. The acknowledge between an event user and the EVSYS clears the CHSTATUS.CHBUSYn bit before this information is fully propagated in the EVSYS one GCLK_EVSYS_CHANNEL_n clock cycle later. As a consequence, any generator event occurring on that channel before that extra GCLK_EVSYS_CHANNEL_n clock cycle will trigger the overrun flag.
    Errata reference: 14835
    Fix/Workaround:
    For applications using event generators other than the software event, monitor the OVR flag.
    For applications using the software event generator, wait one GCLK_EVSYS_CHANNEL_n clock cycle after the CHSTATUS.CHBUSYn bit is cleared before issuing a software event.
  2. Using synchronous, spurious overrun can appear with generic clock for the channel always on.
    Errata reference: 14532
    Fix/Workaround:
    - Request the generic clock on demand by setting the CHANNEL.ONDEMAND bit to one.
    - No penalty is introduced.

TC

  1. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15056
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBuf with a new value, the STATUS.xxBUFV flag must be cleared successively two times.

TCC

  1. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15057
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBUF with a new value, the STATUS.xxBUFV flag must be cleared successively two times.
  2. Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) doesn’t work if an upper channel is not in one of these mode. Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN, and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
    Errata reference: 14817
    Fix/Workaround:
    Basic capture mode must be set in lower channel and advance capture mode in upper channel.
    Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN, CC[3]=CAPTMAX
    All capture will be done as expected.

AC

  1. Low power mode (COMPCTRLn.SPEED = 0x0) with Hysteresis enabled (COMPCTRLn.HYSTEN = 0x1) may result in undesired behavior of the AC.
    Errata reference: 15714
    Fix/Workaround:
    Do not use AC Low Power mode (COMPCTRLn.SPEED = 0x0) and hysteresis (COMPCTRLn.HYSTEN = 0x1) together. Use only one of these features to avoid incorrect AC behavior.

ADC

  1. If a synchronized event is received during an ADC conversion, the ADC will not acknowledge the event, causing a stall of the event channel.
    Errata reference: 14795
    Fix/Workaround:
    When using events with the ADC, only the asynchronous path from the Event System must be used.

Die Revision D

Device

  1. The OSC48M accuracy cannot be reached for the whole VDD range.
    Errata reference: 15342
    Fix/Workaround:
    Rev A / B: none
    Rev C: limited VDD range, according to the Electrical Characteristics chapter
    Rev D: write OSCCTRL.CAL48M register, depending on the VDD range used.

DMAC

  1. When using more than one DMA channel and if one of these DMA channels has a linked descriptor, a fetch error can appear on this channel.
    Errata reference: 15670
    Fix/Workaround:
    Do not use linked descriptors, make a software link instead:
    Replace the channel which used linked descriptor by two channels DMA (with linked descriptor disabled) handled by two channels event system:
    - DMA channel 0 transfer completion is able to send a conditional event for DMA channel 1 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 0 and configuration CHCTRLB.EVACT=CBLOCK for channel 1).
    - On the transfer complete reception of the DMA channel 0, immediately re-enable the channel 0.
    - Then DMA channel 1 transfer completion is able to send a conditional event for DMA channel 0 (via event system with configuration of BTCTRL.EVOSEL=BLOCK for channel 1 and configuration CHCTRLB.EVACT=CBLOCK for channel 0).
    - On the transfer complete reception of the DMA channel 1, immediately re-enable the channel 1.
    - The mechanism can be launched by sending a software event on the DMA channel 0.

EIC

  1. When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit.
    Errata reference: 15278
    Fix/Workaround:
    Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts.

NVMCTRL

  1. The RWW EEPROM cache is not invalidated when performing write or erase operations. Reading RWWEE cached data can result in outdated data.
    Errata reference: 14633
    Fix/Workaround:
    When the RWW EEPROM Cache is on (CTRLB.CACHEDIS=0x2 or CTRLB.CACHEDIS=0x3) invalidate the cache by issuing the INVALL NVMCTRL command immediately after issuing a RWW EEPROM write or erase operation.

EVSYS

  1. The acknowledge between an event user and the EVSYS clears the CHSTATUS.CHBUSYn bit before this information is fully propagated in the EVSYS one GCLK_EVSYS_CHANNEL_n clock cycle later. As a consequence, any generator event occurring on that channel before that extra GCLK_EVSYS_CHANNEL_n clock cycle will trigger the overrun flag.
    Errata reference: 14835
    Fix/Workaround:
    For applications using event generators other than the software event, monitor the OVR flag.
    For applications using the software event generator, wait one GCLK_EVSYS_CHANNEL_n clock cycle after the CHSTATUS.CHBUSYn bit is cleared before issuing a software event.
  2. Using synchronous, spurious overrun can appear with generic clock for the channel always on.
    Errata reference: 14532
    Fix/Workaround:
    - Request the generic clock on demand by setting the CHANNEL.ONDEMAND bit to one.
    - No penalty is introduced.

TC

  1. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15056
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBuf with a new value, the STATUS.xxBUFV flag must be cleared successively two times.

TCC

  1. When clearing STATUS.xxBUFV flag, SYNCBUSY is released before the register is restored to its appropriate value.
    Errata reference: 15057
    Fix/Workaround:
    To ensure that the register value is properly restored before updating this same register through xx or xxBUF with a new value, the STATUS.xxBUFV flag must be cleared successively two times.
  2. Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) doesn’t work if an upper channel is not in one of these mode. Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN, and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
    Errata reference: 14817
    Fix/Workaround:
    Basic capture mode must be set in lower channel and advance capture mode in upper channel.
    Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN, CC[3]=CAPTMAX
    All capture will be done as expected.

AC

  1. Low power mode (COMPCTRLn.SPEED = 0x0) with Hysteresis enabled (COMPCTRLn.HYSTEN = 0x1) may result in undesired behavior of the AC.
    Errata reference: 15714
    Fix/Workaround:
    Do not use AC Low Power mode (COMPCTRLn.SPEED = 0x0) and hysteresis (COMPCTRLn.HYSTEN = 0x1) together. Use only one of these features to avoid incorrect AC behavior.

ADC

  1. If a synchronized event is received during an ADC conversion, the ADC will not acknowledge the event, causing a stall of the event channel.
    Errata reference: 14795
    Fix/Workaround:
    When using events with the ADC, only the asynchronous path from the Event System must be used.