SLEEPCFG

Name:: SLEEPCFG
Offset:: 0x01
Reset:: 0x00
Access:: PAC Write-Protection

Bit7	6	5	4	3	2	1	0
					SLEEPMODE[2:0]
Access					R/W	R/W	R/W
Reset					0	0	0

Bits 2:0 – SLEEPMODE[2:0]: Sleep Mode

Sleep Mode

Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software has to make sure the SLEEPCFG register reads the wanted value before issuing Wait For Interrupt (WFI) instruction.

Value	Name	Definition
0x0	Reserved	Reserved
0x1	Reserved	Reserved
0x2	IDLE	CPU, AHBx and APBx clocks are OFF
0x3	Reserved	Reserved
0x4	STANDBY	ALL clocks are OFF, unless requested by sleepwalking peripheral
0x5 - 0x7	Reserved	Reserved