Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x0C
Reset:
0x00
Access:
PAC Write-Protection
Bit76543210
ERRORREADY
AccessR/WR/W
Reset00

Bit 1 – ERROR: Error Interrupt Enable

Error Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the ERROR interrupt enable.

This bit will read as the current value of the ERROR interrupt enable.

Bit 0 – READY: NVM Ready Interrupt Enable

NVM Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the READY interrupt enable.

This bit will read as the current value of the READY interrupt enable.