| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| BBIASHS | |||||||
| Access | R/W | ||||||
| Reset | 1 | ||||||
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VREGSMOD[1:0] | |||||||
| AccessR/W | R/W | ||||||
| Reset0 | 0 | ||||||
Back Bias for HMCRAMCHS
Refer to RAM Automatic Low Power Mode for details.
| Value | Description |
|---|---|
| 0 | No Back Biasing Mode |
| 1 | Standby Back Biasing Mode |
VREG Switching Mode
Refer to for Regulator Automatic Low Power Mode details.
| Value | Name | Description |
|---|---|---|
| 0x0 | AUTO | Automatic Mode |
| 0x1 | PERFORMANCE | Performance oriented |
| 0x2 | LP | Low Power consumption oriented |
| 0x9 | Reserved | Reserved |